| /external/llvm/test/CodeGen/Mips/ |
| D | atomic.ll | 125 ; CHECK-EL: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
127 ; CHECK-EL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
151 ; CHECK-EB: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
153 ; CHECK-EB: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
182 ; CHECK-EL: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
184 ; CHECK-EL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
208 ; CHECK-EB: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
210 ; CHECK-EB: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
240 ; CHECK-EL: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
242 ; CHECK-EL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
[all …]
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | 2010-03-09-indirect-call.ll | 5 ; Indirect calls must use R12 on Darwin (i.e., R12 must contain the address of
|
| /external/llvm/test/CodeGen/ARM/ |
| D | unaligned_load_store.ll | 13 ; EXPANDED: ldrb [[R12:r[0-9]+]]
16 ; EXPANDED: strb [[R12]]
|
| /external/llvm/test/CodeGen/Thumb2/ |
| D | 2010-08-10-VarSizedAllocaBug.ll | 10 ; CHECK: sub.w [[R12:r[0-9]+]], r4, #1000
11 ; CHECK: mov sp, [[R12]]
|
| /external/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineAndOrXor.cpp | 568 Value *R11,*R12; in foldLogOpOfMaskedICmpsHelper() local
570 if (decomposeBitTestICmp(RHS, RHSCC, R11, R12, R2)) { in foldLogOpOfMaskedICmpsHelper()
572 A = R11; D = R12; in foldLogOpOfMaskedICmpsHelper()
573 } else if (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22) { in foldLogOpOfMaskedICmpsHelper()
574 A = R12; D = R11; in foldLogOpOfMaskedICmpsHelper()
579 } else if (match(R1, m_And(m_Value(R11), m_Value(R12)))) { in foldLogOpOfMaskedICmpsHelper()
581 A = R11; D = R12; E = R2; ok = true; in foldLogOpOfMaskedICmpsHelper()
582 } else if (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22) { in foldLogOpOfMaskedICmpsHelper()
583 A = R12; D = R11; E = R2; ok = true; in foldLogOpOfMaskedICmpsHelper()
592 if (!ok && match(R2, m_And(m_Value(R11), m_Value(R12)))) { in foldLogOpOfMaskedICmpsHelper()
[all …]
|
| /external/kernel-headers/original/asm-x86/ |
| D | ptrace-abi.h | 31 #define R12 24 macro
|
| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.cpp | 92 case X86::ECX: case X86::R12: return 2; in getCompactUnwindRegNum()
576 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: in getX86SubSuperRegister()
613 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: in getX86SubSuperRegister()
649 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: in getX86SubSuperRegister()
685 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: in getX86SubSuperRegister()
686 return X86::R12; in getX86SubSuperRegister()
|
| D | X86CallingConv.td | 312 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
547 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
552 def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
556 R11, R12, R13, R14, R15, RBP,
560 def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12,
565 R12, R13, R14, R15,
|
| D | X86RegisterInfo.td | 144 def R12 : X86Reg<"r12", 12, [R12D]>, DwarfRegNum<[12, -2, -2]>;
308 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
311 // Allocate R12 and R13 last, as these require an extra byte when
340 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430CallingConv.td | 19 // i16 are returned in registers R15, R14, R13, R12
|
| /external/llvm/lib/Target/ARM/ |
| D | Thumb1RegisterInfo.cpp | 522 .addReg(ARM::R12, RegState::Define) in saveScavengerRegister()
535 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::R12)) { in saveScavengerRegister()
543 if (MO.getReg() == ARM::R12) { in saveScavengerRegister()
552 addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill)); in saveScavengerRegister()
|
| D | ARMRegisterInfo.td | 74 def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>;
254 def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R9, R12)> {
337 [(add R0, R2, R4, R6, R8, R10, R12),
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 76 def R12 : Ri<12, "r12">, DwarfRegNum<[12]>;
109 def D6 : Rd<12, "r13:12", [R12, R13]>, DwarfRegNum<[44]>;
|
| /external/valgrind/main/coregrind/m_sigframe/ |
| D | sigframe-arm-linux.c | 150 SC2(ip,R12); in synth_ucontext()
329 REST(ip,R12); in VG_()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 509 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R12) in emitPrologue()
511 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R12) in emitPrologue()
512 .addReg(PPC::R12, RegState::Kill) in emitPrologue()
516 .addReg(PPC::R12, RegState::Kill); in emitPrologue()
1302 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12) in spillCalleeSavedRegisters()
1307 .addReg(PPC::R12, in spillCalleeSavedRegisters()
1338 PPC::R12), in restoreCRs()
1341 MoveReg = PPC::R12; in restoreCRs()
|
| D | PPCAsmPrinter.cpp | 949 .addReg(PPC::R12) in EmitFunctionStubs()
953 OutStreamer.EmitInstruction(MCInstBuilder(PPC::MTCTR).addReg(PPC::R12)); in EmitFunctionStubs()
1003 .addReg(PPC::R12) in EmitFunctionStubs()
1008 OutStreamer.EmitInstruction(MCInstBuilder(PPC::MTCTR).addReg(PPC::R12)); in EmitFunctionStubs()
|
| /external/valgrind/main/VEX/orig_ppc32/ |
| D | return0.orig | 248 5: PUTL t4, R12
258 11: GETL R12, t10
561 6: PUTL t2, R12
565 8: GETL R12, t4
571 12: GETL R12, t6
907 8: PUTL t6, R12
911 10: GETL R12, t8
1040 10: PUTL t6, R12
1153 68: GETL R12, t54
1336 41: PUTL t24, R12
[all …]
|
| D | date.orig | 248 5: PUTL t4, R12
258 11: GETL R12, t10
561 6: PUTL t2, R12
565 8: GETL R12, t4
571 12: GETL R12, t6
907 8: PUTL t6, R12
911 10: GETL R12, t8
1040 10: PUTL t6, R12
1153 68: GETL R12, t54
1336 41: PUTL t24, R12
[all …]
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 173 ENTRY(R12) \
191 ENTRY(R12) \
|
| /external/valgrind/main/VEX/auxprogs/ |
| D | genoffsets.c | 112 GENOFFSET(AMD64,amd64,R12); in foo()
|
| /external/llvm/test/CodeGen/X86/ |
| D | ghc-cc64.ll | 7 @hp = external global i64 ; assigned to register: R12
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | AMDILRegisterInfo.td | 34 def R12 : AMDILReg<12, "r12">, DwarfRegNum<[12]>;
|
| /external/llvm/lib/Target/R600/ |
| D | AMDILRegisterInfo.td | 34 def R12 : AMDILReg<12, "r12">, DwarfRegNum<[12]>;
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILRegisterInfo.td | 34 def R12 : AMDILReg<12, "r12">, DwarfRegNum<[12]>;
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86BaseInfo.h | 669 case X86::R12: case X86::R13: case X86::R14: case X86::R15: in isX86_64ExtendedReg()
|