| /external/llvm/test/CodeGen/Mips/ |
| D | atomic.ll | 120 ; CHECK-EL: sllv $[[R9:[0-9]+]], $4, $[[R4]]
124 ; CHECK-EL: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
146 ; CHECK-EB: sllv $[[R9:[0-9]+]], $4, $[[R5]]
150 ; CHECK-EB: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
177 ; CHECK-EL: sllv $[[R9:[0-9]+]], $4, $[[R4]]
181 ; CHECK-EL: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
203 ; CHECK-EB: sllv $[[R9:[0-9]+]], $4, $[[R5]]
207 ; CHECK-EB: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
234 ; CHECK-EL: sllv $[[R9:[0-9]+]], $4, $[[R4]]
238 ; CHECK-EL: and $[[R18:[0-9]+]], $[[R10]], $[[R9]]
[all …]
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.td | 35 def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
49 R4, R5, R6, R7, R8, R9, R10,
56 R4, R5, R6, R7, R8, R9, R10,
|
| D | XCoreRegisterInfo.cpp | 66 XCore::R8, XCore::R9, XCore::R10, XCore::LR, in getCalleeSavedRegs()
|
| /external/valgrind/main/VEX/orig_ppc32/ |
| D | return0.orig | 100 43: PUTL t30, R9
147 76: GETL R9, t58
152 79: GETL R9, t60
154 81: PUTL t60, R9
172 1: GETL R9, t2
177 4: GETL R9, t4
179 6: PUTL t4, R9
315 52: PUTL t40, R9
319 54: GETL R9, t42
326 59: GETL R9, t46
[all …]
|
| D | date.orig | 100 43: PUTL t30, R9
147 76: GETL R9, t58
152 79: GETL R9, t60
154 81: PUTL t60, R9
172 1: GETL R9, t2
177 4: GETL R9, t4
179 6: PUTL t4, R9
315 52: PUTL t40, R9
319 54: GETL R9, t42
326 59: GETL R9, t46
[all …]
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMCallingConv.td | 99 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
194 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
201 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
205 // iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved register.
207 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
210 (sub CSR_AAPCS_ThisReturn, R9))>;
|
| D | ARMBaseRegisterInfo.h | 45 case R8: case R9: case R10: case R11: in isARMArea1Register()
56 case R8: case R9: case R10: case R11: in isARMArea2Register()
|
| D | ARMRegisterInfo.td | 71 def R9 : ARMReg< 9, "r9">, DwarfRegNum<[9]>;
254 def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R9, R12)> {
338 (add R1, R3, R5, R7, R9, R11, SP)]>;
|
| /external/kernel-headers/original/asm-x86/ |
| D | ptrace-abi.h | 37 #define R9 64 macro
|
| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.cpp | 570 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: in getX86SubSuperRegister()
607 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: in getX86SubSuperRegister()
643 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: in getX86SubSuperRegister()
679 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: in getX86SubSuperRegister()
680 return X86::R9; in getX86SubSuperRegister()
|
| D | X86CallingConv.td | 207 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
286 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ],
289 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
295 [RCX , RDX , R8 , R9 ]>>,
312 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
479 CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>,
555 def CSR_MostRegs_64 : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
|
| D | X86RegisterInfo.td | 141 def R9 : X86Reg<"r9", 9, [R9D]>, DwarfRegNum<[ 9, -2, -2]>;
339 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
366 R8, R9, R11, RIP)>;
368 R8, R9, R11)>;
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 73 def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
107 def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>;
|
| /external/valgrind/main/coregrind/m_sigframe/ |
| D | sigframe-arm-linux.c | 147 SC2(r9,R9); in synth_ucontext()
326 REST(r9,R9); in VG_()
|
| D | sigframe-amd64-linux.c | 346 SC2(r9,R9); in synth_ucontext()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCallingConv.td | 28 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
50 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
|
| /external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/pkb/en-US/ |
| D | en-US_lh0_kdt_mgc2.pkb | 69 �������8���[� �����ͅ���k� �R�x0e_������Xl��@���`YD�R9��
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 170 ENTRY(R9) \
188 ENTRY(R9) \
|
| /external/valgrind/main/VEX/auxprogs/ |
| D | genoffsets.c | 109 GENOFFSET(AMD64,amd64,R9); in foo()
|
| /external/llvm/test/CodeGen/X86/ |
| D | ghc-cc64.ll | 13 @r6 = external global i64 ; assigned to register: R9
|
| /external/bison/tests/ |
| D | output.at | 322 "0R9d" [label="R9", fillcolor=5, shape=diamond, style=filled]
464 0 -> "0R9" [label="['?', '!']", style=solid]
465 "0R9" [label="R9", fillcolor=3, shape=diamond, style=filled]
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | AMDILRegisterInfo.td | 31 def R9 : AMDILReg<9, "r9">, DwarfRegNum<[9]>;
|
| /external/llvm/lib/Target/R600/ |
| D | AMDILRegisterInfo.td | 31 def R9 : AMDILReg<9, "r9">, DwarfRegNum<[9]>;
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILRegisterInfo.td | 31 def R9 : AMDILReg<9, "r9">, DwarfRegNum<[9]>;
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86BaseInfo.h | 668 case X86::R8: case X86::R9: case X86::R10: case X86::R11: in isX86_64ExtendedReg()
|