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Searched refs:RAX (Results 1 – 25 of 42) sorted by relevance

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/external/llvm/test/CodeGen/X86/
Dabi-isel.ll56 ; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r..]]
57 ; LINUX-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e..]]
85 ; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), [[RAX:%r..]]
86 ; DARWIN-64-STATIC-NEXT: movl ([[RAX]]), [[EAX:%e..]]
92 ; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), [[RAX:%r..]]
93 ; DARWIN-64-DYNAMIC-NEXT: movl ([[RAX]]), [[EAX:%e..]]
99 ; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), [[RAX:%r..]]
100 ; DARWIN-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e..]]
128 ; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
129 ; LINUX-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e.x]]
[all …]
Dobject-size.ll15 ; X64: movabsq $-1, [[RAX:%r..]]
16 ; X64: cmpq $-1, [[RAX]]
D2009-09-19-earlyclobber.ll4 ; Registers other than RAX, RCX are OK, but they must be different.
D2010-02-12-CoalescerBug-Impdef.ll5 ; After coalescing %RAX with a virtual register, this instruction was rematted:
9 ; This instruction silently defined %RAX, and when rematting removed the
10 ; instruction, the live interval for %RAX was not properly updated. The valno
13 ; The fix is to implicitly define %RAX when coalescing:
15 ; %EAX<def> = MOV32rr %reg1070<kill>, %RAX<imp-def>
D2010-04-08-CoalescerBug.ll5 ; %RDI<def,dead> = MOV64rr %RAX<kill>, %EDI<imp-def>
Dtailcall-64.ll184 ; CHECK: leaq (%rsi,%rsi,4), %[[RAX:r..]]
185 ; CHECK: jmpq *16(%{{r..}},%[[RAX]],8) # TAILCALL
Dmisched-new.ll17 ; After coalescing, we have a dead superreg (RAX) definition.
/external/llvm/test/MC/X86/
Dintel-syntax.s19 mov RAX, QWORD PTR [RSP]
25 mov EAX, DWORD PTR [RSP + 4*RAX - 24]
65 mov RAX, QWORD PTR FS:[320]
372 shld [RAX], BX
373 shld [RAX], BX, CL
377 shrd [RAX], BX
378 shrd [RAX], BX, CL
443 xchg RAX, RCX
444 xchg RCX, RAX
456 xchg RAX, [ECX]
[all …]
Dintel-syntax-encoding.s25 mov QWORD PTR [RSP - 16], RAX
/external/llvm/lib/Target/X86/
DX86InstrSVM.td35 let Uses = [RAX] in
43 let Uses = [RAX] in
51 let Uses = [RAX] in
59 let Uses = [RAX, ECX] in
DX86InstrArithmetic.td78 // RAX,RDX = RAX*GR64
79 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
82 [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/],
104 // RAX,RDX = RAX*[mem64]
105 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
123 // RAX,RDX = RAX*GR64
124 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
142 // RAX,RDX = RAX*[mem64]
143 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
306 // RDX:RAX/r64 = RAX,RDX
[all …]
DX86InstrExtension.td30 let Defs = [RAX], Uses = [EAX] in
32 "{cltq|cdqe}", []>; // RAX = signext(EAX)
34 let Defs = [RAX,RDX], Uses = [RAX] in
36 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
DX86RegisterInfo.cpp540 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegister()
552 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegister()
589 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegister()
625 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegister()
661 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegister()
662 return X86::RAX; in getX86SubSuperRegister()
DX86RegisterInfo.td129 def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>;
339 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
363 def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>;
365 def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI,
367 def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX,
386 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
390 // to clear upper 32-bits of RAX so is not a NOP.
DX86InstrSystem.td17 let Defs = [RAX, RDX] in
21 let Defs = [RAX, RCX, RDX] in
442 let Defs = [RDX, RAX], Uses = [RCX] in
445 let Uses = [RDX, RAX, RCX] in
448 let Uses = [RDX, RAX] in {
466 let Defs = [RAX, RDI], Uses = [RDX, RDI] in
479 let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
483 let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
DX86MCInstLower.cpp247 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortImmForm()
274 if (Op0 == X86::RAX && Op1 == X86::EAX) in SimplifyMOVSX()
308 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortMoveForm()
602 OutMI.addOperand(MCOperand::CreateReg(X86::RAX)); in Lower()
DX86FrameLowering.cpp103 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI, in findDeadCallerSavedReg()
168 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX) in emitSPUpdate()
528 if (Reg == (Is64Bit ? X86::RAX : X86::EAX)) { in getCompactUnwindEncoding()
899 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX) in emitPrologue()
922 .addReg(X86::RAX) in emitPrologue()
1561 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10); in adjustForSegmentedStacks()
DX86CallingConv.td38 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
138 // The X86-Win64 calling convention always returns __m64 values in RAX.
151 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>>
550 def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>;
DX86InstrControl.td257 // ___chkstk(Mingw64): clobber R10, R11, RAX and EFLAGS, and update RSP.
258 let Defs = [RAX, R10, R11, RSP, EFLAGS],
DX86SelectionDAGInfo.cpp106 ValReg = X86::RAX; in EmitTargetCodeForMemset()
DX86InstrCompiler.td122 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
370 let Uses = [RAX,RCX,RDI] in
375 let Uses = [RAX,RCX,RDI] in
408 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
438 let Defs = [RAX, EFLAGS],
524 let Defs = [EFLAGS, RAX] in
743 let Defs = [RAX, EFLAGS], Uses = [RAX] in
757 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
/external/kernel-headers/original/asm-x86/
Dptrace-abi.h39 #define RAX 80 macro
/external/lzma/Asm/x86/
D7zAsm.asm62 r0 equ RAX
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h161 ENTRY(RAX) \
179 ENTRY(RAX) \
/external/valgrind/main/VEX/auxprogs/
Dgenoffsets.c100 GENOFFSET(AMD64,amd64,RAX); in foo()

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