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Searched refs:RSP (Results 1 – 25 of 26) sorted by relevance

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/external/llvm/test/MC/X86/
Dintel-syntax.s9 mov DWORD PTR [RSP - 4], 257
11 mov DWORD PTR [RSP + 4], 258
13 mov QWORD PTR [RSP - 16], 123
15 mov BYTE PTR [RSP - 17], 97
17 mov EAX, DWORD PTR [RSP - 4]
19 mov RAX, QWORD PTR [RSP]
21 mov DWORD PTR [RSP - 4], -4
25 mov EAX, DWORD PTR [RSP + 4*RAX - 24]
Dintel-syntax-2.s6 mov DWORD PTR [RSP - 4], 257
Dintel-syntax-encoding.s25 mov QWORD PTR [RSP - 16], RAX
/external/llvm/lib/Target/X86/
DX86RegisterInfo.cpp74 StackPtr = X86::RSP; in X86RegisterInfo()
318 for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid(); in getReservedRegs()
538 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegister()
566 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegister()
603 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegister()
639 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegister()
675 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegister()
676 return X86::RSP; in getX86SubSuperRegister()
DX86InstrControl.td231 // RSP is marked as a use to prevent stack-pointer assignments that appear
234 let isCall = 1, Uses = [RSP], SchedRW = [WriteJump] in {
257 // ___chkstk(Mingw64): clobber R10, R11, RAX and EFLAGS, and update RSP.
258 let Defs = [RAX, R10, R11, RSP, EFLAGS],
259 Uses = [RSP] in {
267 isCodeGenOnly = 1, Uses = [RSP], usesCustomInserter = 1,
DX86CompilationCallback_Win64.asm20 ; Save RSP.
DX86RegisterInfo.td136 def RSP : X86Reg<"rsp", 4, [ESP]>, DwarfRegNum<[7, -2, -2]>;
340 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
386 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
396 // GR64_NOSP - GR64 registers except RSP (and RIP).
397 def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>;
404 // GR64_NOREX_NOSP - GR64_NOREX registers except RSP.
DX86InstrInfo.td275 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
823 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
883 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
902 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1,
912 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
915 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
DX86InstrCompiler.td56 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
61 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
122 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
405 // All calls clobber the non-callee saved registers. RSP is marked as
413 Uses = [RSP] in {
439 Uses = [RSP, RDI],
DX86FrameLowering.cpp1480 ScratchReg = X86::RSP; in adjustForSegmentedStacks()
1482 BuildMI(checkMBB, DL, TII.get(X86::LEA64r), ScratchReg).addReg(X86::RSP) in adjustForSegmentedStacks()
1697 SPReg = X86::RSP; in adjustForHiPEPrologue()
DX86CodeEmitter.cpp549 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); in emitMemModRMByte()
/external/kernel-headers/original/asm-x86/
Dptrace-abi.h50 #define RSP 152 macro
/external/chromium_org/third_party/yasm/source/patched-yasm/modules/objfmts/win64/tests/
Dsce1.asm15 [savereg rdi, 010h]; you can still use RSP as the base of the frame
Dsce3.asm15 [savereg rdi, 010h]; you can still use RSP as the base of the frame
Dsce3.masm18 .savereg rdi, 010h; you can still use RSP as the base of the frame
/external/lzma/Asm/x86/
D7zAsm.asm66 r4 equ RSP
/external/valgrind/main/VEX/auxprogs/
Dgenoffsets.c106 GENOFFSET(AMD64,amd64,RSP); in foo()
/external/valgrind/main/coregrind/m_sigframe/
Dsigframe-amd64-linux.c360 SC2(rsp,RSP); in synth_ucontext()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp293 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP; in createX86MCAsmInfo()
DX86MCCodeEmitter.cpp462 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); in EmitMemModRMByte()
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h183 ENTRY(RSP) \
/external/llvm/docs/
DTableGenFundamentals.rst181 RDX, RIP, RSI, RSP, SI, SIL, SP, SPL, ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
DCodeGenerator.rst1465 immediately after the return address, then ``ESP/RSP`` is moved to
1466 ``EBP/RBP``. Thus to unwind, ``ESP/RSP`` is restored with the current
1489 ``ESP/RSP``. Then the return is done by popping the stack into the PC. All
/external/strace/
Dprocess.c2693 { 8*RSP, "8*RSP" },
/external/valgrind/main/memcheck/
Dmc_machine.c569 if (o == GOF(RSP) && is1248) return o; in get_otrack_shadow_offset_wrk()

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