| /external/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 61 int MCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { in getDwarfRegNum() argument
65 DwarfLLVMRegPair Key = { RegNum, 0 }; in getDwarfRegNum()
67 if (I == M+Size || I->FromReg != RegNum) in getDwarfRegNum()
72 int MCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const { in getLLVMRegNum() argument
76 DwarfLLVMRegPair Key = { RegNum, 0 }; in getLLVMRegNum()
78 assert(I != M+Size && I->FromReg == RegNum && "Invalid RegNum"); in getLLVMRegNum()
82 int MCRegisterInfo::getSEHRegNum(unsigned RegNum) const { in getSEHRegNum()
83 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum); in getSEHRegNum()
84 if (I == L2SEHRegs.end()) return (int)RegNum; in getSEHRegNum()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 179 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
252 unsigned RegNum; member
317 return Reg.RegNum; in getReg()
349 static MipsOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { in CreateReg() argument
351 Op->Reg.RegNum = RegNum; in CreateReg()
379 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum)); in addRegAsmOperands()
900 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) { in matchRegisterByNumber() argument
902 if (RegNum > 31) in matchRegisterByNumber()
905 return getReg(RegClass, RegNum); in matchRegisterByNumber()
910 int RegNum = -1; in tryParseRegister() local
[all …]
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 137 IdentifyRegister(unsigned &RegNum, SMLoc &RegEndLoc, StringRef &LayoutSpec,
182 unsigned RegNum; member
232 return Reg.RegNum; in getReg()
790 static AArch64Operand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { in CreateReg() argument
792 Op->Reg.RegNum = RegNum; in CreateReg()
796 static AArch64Operand *CreateWrappedReg(unsigned RegNum, SMLoc S, SMLoc E) { in CreateWrappedReg() argument
798 Op->Reg.RegNum = RegNum; in CreateWrappedReg()
1528 AArch64AsmParser::IdentifyRegister(unsigned &RegNum, SMLoc &RegEndLoc, in IdentifyRegister() argument
1539 RegNum = MatchRegisterName(LowerReg.substr(0, DotPos)); in IdentifyRegister()
1540 if (RegNum == AArch64::NoRegister) { in IdentifyRegister()
[all …]
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.cpp | 157 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg); in printSavedRegsBitmask() local
159 FPUBitmask |= (3 << RegNum); in printSavedRegsBitmask()
165 FPUBitmask |= (1 << RegNum); in printSavedRegsBitmask()
172 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg); in printSavedRegsBitmask() local
173 CPUBitmask |= (1 << RegNum); in printSavedRegsBitmask()
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 381 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
384 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
388 int getSEHRegNum(unsigned RegNum) const;
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXRegisterInfo.h | 58 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const;
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| D | NVPTXRegisterInfo.cpp | 116 int NVPTXRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { in getDwarfRegNum() argument
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| D | NVPTXAsmPrinter.cpp | 375 unsigned RegNum = RegMap[Reg]; in encodeVirtualRegister() local
397 Ret |= (RegNum & 0x0FFFFFFF); in encodeVirtualRegister()
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| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.h | 65 int getCompactUnwindRegNum(unsigned RegNum, bool isEH) const;
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| D | X86CodeEmitter.cpp | 1474 unsigned RegNum = getX86RegNum(MO.getReg()) << 4; in emitInstruction() local
1476 RegNum |= 1 << 7; in emitInstruction()
1484 RegNum |= Val; in emitInstruction()
1487 emitConstant(RegNum, 1); in emitInstruction()
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| D | X86RegisterInfo.cpp | 89 int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const { in getCompactUnwindRegNum() argument
90 switch (getLLVMRegNum(RegNum, isEH)) { in getCompactUnwindRegNum()
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| /external/clang/lib/Basic/ |
| D | TargetInfo.cpp | 248 if (AddlNames[i].Names[j] == Name && AddlNames[i].RegNum < NumNames) in isValidGCCRegisterName()
301 if (AddlNames[i].Names[j] == Name && AddlNames[i].RegNum < NumNames) in getNormalizedGCCRegisterName()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 359 unsigned RegNum; member
364 unsigned RegNum; member
393 unsigned RegNum; member
552 return Reg.RegNum; in getReg()
1228 .contains(VectorList.RegNum)); in isVecListDPair()
1244 .contains(VectorList.RegNum)); in isVecListDPairSpaced()
1271 .contains(VectorList.RegNum)); in isVecListDPairAllLanes()
1498 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands() local
1499 Inst.addOperand(MCOperand::CreateReg(RegNum)); in addCondCodeOperands()
1871 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); in addAM3OffsetOperands()
[all …]
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| /external/llvm/lib/Target/R600/ |
| D | AMDILCFGStructurizer.cpp | 232 MachineBasicBlock::iterator I, int NewOpcode, int RegNum,
234 void insertCondBranchEnd(MachineBasicBlock *MBB, int NewOpcode, int RegNum);
511 MachineBasicBlock::iterator I, int NewOpcode, int RegNum, in insertCondBranchBefore() argument
517 MachineInstrBuilder(*MF, NewInstr).addReg(RegNum, false); in insertCondBranchBefore()
522 int NewOpcode, int RegNum) { in insertCondBranchEnd() argument
527 MachineInstrBuilder(*MF, NewInstr).addReg(RegNum, false); in insertCondBranchEnd()
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.h | 37 void printRegName(raw_ostream &O, unsigned RegNum) const;
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 1417 unsigned RegNum = GetX86RegNum(MO) << 4; in EncodeInstruction() local
1419 RegNum |= 1 << 7; in EncodeInstruction()
1427 RegNum |= Val; in EncodeInstruction()
1430 EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1, in EncodeInstruction()
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| /external/clang/include/clang/Basic/ |
| D | TargetInfo.h | 573 const unsigned RegNum; member
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| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 485 unsigned RegNum = MO.isUndef() ? UINT_MAX : TRI->getEncodingValue(Reg); in MergeLDR_STR() local
491 ((isNotVFP && RegNum > PRegNum) || in MergeLDR_STR()
492 ((Count < Limit) && RegNum == PRegNum+1))) { in MergeLDR_STR()
494 PRegNum = RegNum; in MergeLDR_STR()
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| D | ARMCodeEmitter.cpp | 1406 unsigned RegNum = II->getRegisterInfo().getEncodingValue(MO.getReg()); in emitLoadStoreMultipleInstruction() local
1408 RegNum < 16); in emitLoadStoreMultipleInstruction()
1409 Binary |= 0x1 << RegNum; in emitLoadStoreMultipleInstruction()
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | AMDILCFGStructurizer.cpp | 382 void addLoopBreakOnReg(LoopT *LoopRep, RegiT RegNum);
383 void addLoopContOnReg(LoopT *LoopRep, RegiT RegNum);
384 void addLoopBreakInitReg(LoopT *LoopRep, RegiT RegNum);
385 void addLoopContInitReg(LoopT *LoopRep, RegiT RegNum);
386 void addLoopEndbranchInitReg(LoopT *LoopRep, RegiT RegNum);
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILCFGStructurizer.cpp | 382 void addLoopBreakOnReg(LoopT *LoopRep, RegiT RegNum);
383 void addLoopContOnReg(LoopT *LoopRep, RegiT RegNum);
384 void addLoopBreakInitReg(LoopT *LoopRep, RegiT RegNum);
385 void addLoopContInitReg(LoopT *LoopRep, RegiT RegNum);
386 void addLoopEndbranchInitReg(LoopT *LoopRep, RegiT RegNum);
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 1281 unsigned RegNum = Registers[i]->EnumValue; in computeUberSets() local
1282 if (AllocatableRegs.count(RegNum)) in computeUberSets()
1285 UberSetIDs.join(0, RegNum); in computeUberSets()
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 969 if (unsigned RegNum = MO2.getReg()) { in printThumbAddrModeRROperand() local
971 printRegName(O, RegNum); in printThumbAddrModeRROperand()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 1835 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs() local
1841 if (RegNum != NumArgRegs && RegNum % 2 == 1) { in CC_PPC32_SVR4_Custom_AlignArgRegs()
1842 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs()
1863 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs() local
1867 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
1868 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
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