Searched refs:RegSize (Results 1 – 6 of 6) sorted by relevance
| /external/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 45 void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
46 void expandStoreACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
49 unsigned Src, unsigned RegSize);
153 unsigned RegSize) { in expandLoadACC() argument
166 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC()
177 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); in expandLoadACC()
182 unsigned RegSize) { in expandStoreACC() argument
195 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC()
207 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize); in expandStoreACC()
223 unsigned Src, unsigned RegSize) { in expandCopyACC() argument
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| D | MipsISelLowering.cpp | 3260 unsigned RegSize = regSize(); in handleByValArg() local
3261 unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize); in handleByValArg()
3262 unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize), in handleByValArg()
3263 RegSize * 2); in handleByValArg()
3269 ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs, in handleByValArg()
3308 unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs(); in allocateRegs() local
3310 assert(!(ByValSize % RegSize) && !(Align % RegSize) && in allocateRegs()
3317 if ((Align > RegSize) && (ByVal.FirstIdx % 2)) { in allocateRegs()
3324 ByValSize -= RegSize, ++I, ++ByVal.NumRegs) in allocateRegs()
3396 unsigned RegSize = CC.regSize(); in passByValArg() local
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.cpp | 429 LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {} in LogicOp()
431 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {} in LogicOp()
433 operator bool() const { return RegSize; } in operator bool()
435 unsigned RegSize, ImmLSB, ImmSize; member
504 if (And.RegSize == 64) in convertToThreeAddress()
515 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB); in convertToThreeAddress()
517 if (isRxSBGMask(Imm, And.RegSize, Start, End)) { in convertToThreeAddress()
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 41 const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes variable
86 unsigned getSize() const { return RegSize; } in getSize()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 720 unsigned RegSize = RegisterVT.getSizeInBits(); in getCopyFromRegs() local
724 if (NumZeroBits == RegSize) { in getCopyFromRegs()
736 if (NumSignBits == RegSize) in getCopyFromRegs()
738 else if (NumZeroBits >= RegSize-1) in getCopyFromRegs()
740 else if (NumSignBits > RegSize-8) in getCopyFromRegs()
742 else if (NumZeroBits >= RegSize-8) in getCopyFromRegs()
744 else if (NumSignBits > RegSize-16) in getCopyFromRegs()
746 else if (NumZeroBits >= RegSize-16) in getCopyFromRegs()
748 else if (NumSignBits > RegSize-32) in getCopyFromRegs()
750 else if (NumZeroBits >= RegSize-32) in getCopyFromRegs()
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| /external/clang/lib/CodeGen/ |
| D | TargetInfo.cpp | 3927 int RegSize; in EmitVAArg() local
3934 RegSize = 8 * (8 - FreeIntRegs); in EmitVAArg()
3941 RegSize = 16 * (8 - FreeVFPRegs); in EmitVAArg()
3979 llvm::ConstantInt::get(CGF.Int32Ty, RegSize), in EmitVAArg()
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