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Searched refs:SCIdx (Results 1 – 3 of 3) sorted by relevance

/external/llvm/utils/TableGen/
DCodeGenSchedule.cpp522 unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, ProcIndices); in collectSchedClasses() local
523 InstrClassMap[(*I)->TheDef] = SCIdx; in collectSchedClasses()
542 unsigned SCIdx = InstrClassMap.lookup((*I)->TheDef); in collectSchedClasses() local
543 if (!SCIdx) { in collectSchedClasses()
547 CodeGenSchedClass &SC = getSchedClass(SCIdx); in collectSchedClasses()
567 const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs; in collectSchedClasses()
693 unsigned SCIdx = Pos->second; in createInstRWClass() local
696 if (ClassInstrs[CIdx].first == SCIdx) in createInstRWClass()
701 ClassInstrs[CIdx].first = SCIdx; in createInstRWClass()
734 unsigned SCIdx = SchedClasses.size(); in createInstRWClass() local
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DSubtargetEmitter.cpp1160 for (unsigned SCIdx = 1, SCEnd = SCTab.size(); SCIdx != SCEnd; ++SCIdx) { in EmitSchedClassTables() local
1161 MCSchedClassDesc &MCDesc = SCTab[SCIdx]; in EmitSchedClassTables()
1162 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx); in EmitSchedClassTables()
1174 if (SCIdx + 1 < SCEnd) in EmitSchedClassTables()
1176 OS << " // #" << SCIdx << '\n'; in EmitSchedClassTables()
DCodeGenSchedule.h384 void inferFromInstRWs(unsigned SCIdx);