| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 732 SETLT, // 1 X 1 0 0 True if less than enumerator
743 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; in isSignedIntSetCC()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSelectCCInfo.td | 43 IntRegs:$fval, SETLT)),
113 DoubleRegs:$fval, SETLT)),
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| /external/llvm/lib/Target/R600/ |
| D | AMDILISelLowering.cpp | 503 ISD::SETLT); in LowerSDIV32()
510 ISD::SETLT); in LowerSDIV32()
605 SDValue r10 = DAG.getSetCC(DL, OVT, r0, DAG.getConstant(0, OVT), ISD::SETLT); in LowerSREM32()
608 SDValue r11 = DAG.getSetCC(DL, OVT, r1, DAG.getConstant(0, OVT), ISD::SETLT); in LowerSREM32()
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| D | AMDGPUISelLowering.cpp | 315 case ISD::SETLT: { in LowerMinMax()
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| D | AMDGPUInstructions.td | 70 case ISD::SETLT: return true;}}}]
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 601 ISD::SETLT); in LowerSDIV32()
608 ISD::SETLT); in LowerSDIV32()
707 SDValue r10 = DAG.getSetCC(DL, OVT, r0, DAG.getConstant(0, OVT), ISD::SETLT); in LowerSREM32()
710 SDValue r11 = DAG.getSetCC(DL, OVT, r1, DAG.getConstant(0, OVT), ISD::SETLT); in LowerSREM32()
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| D | AMDGPUInstructions.td | 67 case ISD::SETLT: return true;}}}]
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 601 ISD::SETLT); in LowerSDIV32()
608 ISD::SETLT); in LowerSDIV32()
707 SDValue r10 = DAG.getSetCC(DL, OVT, r0, DAG.getConstant(0, OVT), ISD::SETLT); in LowerSREM32()
710 SDValue r11 = DAG.getSetCC(DL, OVT, r1, DAG.getConstant(0, OVT), ISD::SETLT); in LowerSREM32()
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| D | AMDGPUInstructions.td | 67 case ISD::SETLT: return true;}}}]
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| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 176 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
195 case ICmpInst::ICMP_SLT: return ISD::SETLT; in getICmpCondCode()
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| D | TargetLoweringBase.cpp | 602 CCs[RTLIB::OLT_F32] = ISD::SETLT; in InitCmpLibcallCCs()
603 CCs[RTLIB::OLT_F64] = ISD::SETLT; in InitCmpLibcallCCs()
604 CCs[RTLIB::OLT_F128] = ISD::SETLT; in InitCmpLibcallCCs()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 582 case ISD::SETLT: return PPC::PRED_LT; in getPredicateForSetCC()
605 case ISD::SETLT: return 0; // Bit #0 = SETOLT in getCRIdxForSetCC()
648 case ISD::SETLT: in getVCmpInst()
739 case ISD::SETLT: { in SelectSETCC()
772 case ISD::SETLT: { in SelectSETCC()
812 case ISD::SETLT: in SelectSETCC()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 1600 case ISD::SETLT: return A64CC::LT; in IntCCToA64CC()
1646 case ISD::SETLT: in getSelectableIntSetCC()
1649 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; in getSelectableIntSetCC()
1663 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; in getSelectableIntSetCC()
1705 case ISD::SETLT: in FPCCToA64CC()
2360 case ISD::SETLT: in LowerVectorSETCC()
2425 case ISD::SETLT: in LowerVectorSETCC()
2426 CC = ISD::SETLT; in LowerVectorSETCC()
2444 CC = ISD::SETLT; in LowerVectorSETCC()
2466 CC = ISD::SETLT; in LowerVectorSETCC()
[all …]
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| D | AArch64InstrNEON.td | 711 defm CMLTvvi : NeonI_cmpz_sizes<0b0, 0b01010, "cmlt", SETLT>;
783 defm FCMLTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01110, "fcmlt", SETLT>;
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 127 case ISD::SETLT: in softenSetCCOperands()
1254 case ISD::SETLT: in SimplifySetCC()
1420 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); in SimplifySetCC()
1423 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) in SimplifySetCC()
1436 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) in SimplifySetCC()
1440 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) in SimplifySetCC()
1458 ISD::SETLT); in SimplifySetCC()
1797 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X in SimplifySetCC()
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| D | SelectionDAGDumper.cpp | 304 case ISD::SETLT: return "setlt"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 851 case ISD::SETLT: in PromoteSetCCOperands()
2542 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 in IntegerExpandSetCCOperands()
2553 case ISD::SETLT: in IntegerExpandSetCCOperands()
2590 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || in IntegerExpandSetCCOperands()
2824 ISD::SETLT); in ExpandIntOp_UINT_TO_FP()
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| D | LegalizeDAG.cpp | 1551 ISD::SETLT); in ExpandFCOPYSIGN()
1652 case ISD::SETLT: in LegalizeSetCCCondCode()
2337 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT); in ExpandLegalINT_TO_FP()
2376 ISD::SETLT); in ExpandLegalINT_TO_FP()
2924 Tmp1, ISD::SETLT); in ExpandNode()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 450 case ISD::SETLT: in isLegalDSPCondCode()
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| D | MipsDSPInstrInfo.td | 1360 def : DSPSetCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1373 def : DSPSelectCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 503 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
861 (setcc node:$lhs, node:$rhs, SETLT)>;
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1200 case ISD::SETLT: return SPCC::ICC_L; in IntCondCCodeToICC()
1220 case ISD::SETLT: in FPCondCCodeToFCC()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 3403 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { in TranslateX86CC()
3407 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { in TranslateX86CC()
3419 case ISD::SETLT: return X86::COND_L; in TranslateX86CC()
3466 case ISD::SETLT: return X86::COND_B; in TranslateX86CC()
8632 ISD::SETLT); in LowerUINT_TO_FP()
9615 case ISD::SETLT: in translateX86FSETCC()
9723 case ISD::SETLT: Swap = true; in LowerVSETCC()
10788 CC = ISD::SETLT; in LowerINTRINSIC_WO_CHAIN()
10818 CC = ISD::SETLT; in LowerINTRINSIC_WO_CHAIN()
15888 case ISD::SETLT: in matchIntegerMINMAX()
[all …]
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 764 case ISD::SETLT: in EmitCMP()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1186 case ISD::SETLT: return ARMCC::LT; in IntCCToARMCC()
1215 case ISD::SETLT: in FPCCToARMCC()
3047 case ISD::SETLT: in getARMCmp()
3050 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; in getARMCmp()
3064 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; in getARMCmp()
4026 case ISD::SETLT: Swap = true; // Fallthrough in LowerVSETCC()
4062 case ISD::SETLT: Swap = true; in LowerVSETCC()
9723 case ISD::SETLT: in PerformSELECT_CCCombine()
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