/external/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 716 SETOLE, // 0 1 0 1 True if ordered and less than or equal enumerator
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/external/llvm/lib/CodeGen/ |
D | Analysis.cpp | 157 case FCmpInst::FCMP_OLE: return ISD::SETOLE; in getFCmpCondCode() 177 case ISD::SETOLE: case ISD::SETULE: return ISD::SETLE; in getFCmpCodeWithoutNaN()
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
D | AMDGPUInstructions.td | 73 case ISD::SETOLE: case ISD::SETULE:
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D | AMDILISelLowering.cpp | 134 setOperationAction(ISD::SETOLE, VT, Expand); in InitAMDILLowering()
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/external/mesa3d/src/gallium/drivers/radeon/ |
D | AMDGPUInstructions.td | 73 case ISD::SETOLE: case ISD::SETULE:
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D | AMDILISelLowering.cpp | 134 setOperationAction(ISD::SETOLE, VT, Expand); in InitAMDILLowering()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCISelDAGToDAG.cpp | 573 case ISD::SETOLE: in getPredicateForSetCC() 620 case ISD::SETOLE: in getCRIdxForSetCC() 678 case ISD::SETOLE: in getVCmpInst() 836 case ISD::SETOLE: in SelectSETCC()
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D | PPCISelLowering.cpp | 311 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); in PPCTargetLowering() 312 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); in PPCTargetLowering() 4696 case ISD::SETOLE: in LowerSELECT_CC() 4736 case ISD::SETOLE: in LowerSELECT_CC()
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonISelLowering.cpp | 1134 setCondCodeAction(ISD::SETOLE, MVT::f32, Legal); in HexagonTargetLowering() 1135 setCondCodeAction(ISD::SETOLE, MVT::f64, Legal); in HexagonTargetLowering() 1236 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); in HexagonTargetLowering() 1239 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); in HexagonTargetLowering()
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/external/llvm/lib/Target/R600/ |
D | AMDGPUISelLowering.cpp | 312 case ISD::SETOLE: in LowerMinMax()
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D | AMDGPUInstructions.td | 76 case ISD::SETOLE: case ISD::SETULE:
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D | AMDILISelLowering.cpp | 123 setOperationAction(ISD::SETOLE, VT, Expand); in InitAMDILLowering()
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D | R600ISelLowering.cpp | 888 case ISD::SETOLE: in LowerSELECT_CC()
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | SelectionDAGDumper.cpp | 289 case ISD::SETOLE: return "setole"; in getOperationName()
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D | TargetLowering.cpp | 133 case ISD::SETOLE: in softenSetCCOperands() 1582 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType())) in SimplifySetCC() 1583 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); in SimplifySetCC() 1585 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType())) in SimplifySetCC()
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D | SelectionDAG.cpp | 1570 case ISD::SETOLE: in FoldSetCC() 1625 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || in FoldSetCC()
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D | LegalizeDAG.cpp | 1631 case ISD::SETOLE: in LegalizeSetCCCondCode()
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/external/llvm/include/llvm/Target/ |
D | TargetSelectionDAG.td | 497 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode; 835 (setcc node:$lhs, node:$rhs, SETOLE)>;
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/external/llvm/lib/Target/AArch64/ |
D | AArch64ISelLowering.cpp | 1698 case ISD::SETOLE: CondCode = A64CC::LS; break; in FPCCToA64CC() 2433 case ISD::SETOLE: in LowerVectorSETCC()
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/external/llvm/lib/Target/Sparc/ |
D | SparcISelLowering.cpp | 1225 case ISD::SETOLE: return SPCC::FCC_LE; in FPCondCCodeToFCC()
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/external/llvm/lib/Target/NVPTX/ |
D | NVPTXVector.td | 960 (setcc node:$lhs, node:$rhs, SETOLE)>;
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/external/llvm/lib/Target/ARM/ |
D | ARMISelLowering.cpp | 1208 case ISD::SETOLE: CondCode = ARMCC::LS; break; in FPCCToARMCC() 4029 case ISD::SETOLE: in LowerVSETCC() 9722 case ISD::SETOLE: in PerformSELECT_CCCombine() 9736 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) && in PerformSELECT_CCCombine()
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/external/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 3441 case ISD::SETOLE: in TranslateX86CC() 3461 case ISD::SETOLE: // flipped in TranslateX86CC() 9620 case ISD::SETOLE: SSECC = 2; break; in translateX86FSETCC() 15958 case ISD::SETOLE: in PerformSELECTCombine() 16046 case ISD::SETOLE: in PerformSELECTCombine()
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/external/llvm/lib/Target/Mips/ |
D | MipsISelLowering.cpp | 468 case ISD::SETOLE: return Mips::FCOND_OLE; in condCodeToFCC()
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