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Searched refs:SETOLE (Results 1 – 24 of 24) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h716 SETOLE, // 0 1 0 1 True if ordered and less than or equal enumerator
/external/llvm/lib/CodeGen/
DAnalysis.cpp157 case FCmpInst::FCMP_OLE: return ISD::SETOLE; in getFCmpCondCode()
177 case ISD::SETOLE: case ISD::SETULE: return ISD::SETLE; in getFCmpCodeWithoutNaN()
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
DAMDGPUInstructions.td73 case ISD::SETOLE: case ISD::SETULE:
DAMDILISelLowering.cpp134 setOperationAction(ISD::SETOLE, VT, Expand); in InitAMDILLowering()
/external/mesa3d/src/gallium/drivers/radeon/
DAMDGPUInstructions.td73 case ISD::SETOLE: case ISD::SETULE:
DAMDILISelLowering.cpp134 setOperationAction(ISD::SETOLE, VT, Expand); in InitAMDILLowering()
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp573 case ISD::SETOLE: in getPredicateForSetCC()
620 case ISD::SETOLE: in getCRIdxForSetCC()
678 case ISD::SETOLE: in getVCmpInst()
836 case ISD::SETOLE: in SelectSETCC()
DPPCISelLowering.cpp311 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); in PPCTargetLowering()
312 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); in PPCTargetLowering()
4696 case ISD::SETOLE: in LowerSELECT_CC()
4736 case ISD::SETOLE: in LowerSELECT_CC()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1134 setCondCodeAction(ISD::SETOLE, MVT::f32, Legal); in HexagonTargetLowering()
1135 setCondCodeAction(ISD::SETOLE, MVT::f64, Legal); in HexagonTargetLowering()
1236 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); in HexagonTargetLowering()
1239 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); in HexagonTargetLowering()
/external/llvm/lib/Target/R600/
DAMDGPUISelLowering.cpp312 case ISD::SETOLE: in LowerMinMax()
DAMDGPUInstructions.td76 case ISD::SETOLE: case ISD::SETULE:
DAMDILISelLowering.cpp123 setOperationAction(ISD::SETOLE, VT, Expand); in InitAMDILLowering()
DR600ISelLowering.cpp888 case ISD::SETOLE: in LowerSELECT_CC()
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp289 case ISD::SETOLE: return "setole"; in getOperationName()
DTargetLowering.cpp133 case ISD::SETOLE: in softenSetCCOperands()
1582 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType())) in SimplifySetCC()
1583 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); in SimplifySetCC()
1585 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType())) in SimplifySetCC()
DSelectionDAG.cpp1570 case ISD::SETOLE: in FoldSetCC()
1625 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || in FoldSetCC()
DLegalizeDAG.cpp1631 case ISD::SETOLE: in LegalizeSetCCCondCode()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td497 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
835 (setcc node:$lhs, node:$rhs, SETOLE)>;
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp1698 case ISD::SETOLE: CondCode = A64CC::LS; break; in FPCCToA64CC()
2433 case ISD::SETOLE: in LowerVectorSETCC()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp1225 case ISD::SETOLE: return SPCC::FCC_LE; in FPCondCCodeToFCC()
/external/llvm/lib/Target/NVPTX/
DNVPTXVector.td960 (setcc node:$lhs, node:$rhs, SETOLE)>;
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp1208 case ISD::SETOLE: CondCode = ARMCC::LS; break; in FPCCToARMCC()
4029 case ISD::SETOLE: in LowerVSETCC()
9722 case ISD::SETOLE: in PerformSELECT_CCCombine()
9736 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) && in PerformSELECT_CCCombine()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp3441 case ISD::SETOLE: in TranslateX86CC()
3461 case ISD::SETOLE: // flipped in TranslateX86CC()
9620 case ISD::SETOLE: SSECC = 2; break; in translateX86FSETCC()
15958 case ISD::SETOLE: in PerformSELECTCombine()
16046 case ISD::SETOLE: in PerformSELECTCombine()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp468 case ISD::SETOLE: return Mips::FCOND_OLE; in condCodeToFCC()