Searched refs:SETUEQ (Results 1 – 22 of 22) sorted by relevance
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 720 SETUEQ, // 1 0 0 1 True if unordered or equal enumerator
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| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 161 case FCmpInst::FCMP_UEQ: return ISD::SETUEQ; in getFCmpCondCode()
174 case ISD::SETOEQ: case ISD::SETUEQ: return ISD::SETEQ; in getFCmpCodeWithoutNaN()
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | AMDGPUInstructions.td | 39 case ISD::SETOEQ: case ISD::SETUEQ:
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| D | R600ISelLowering.cpp | 449 case ISD::SETUEQ: in LowerSELECT_CC()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUInstructions.td | 39 case ISD::SETOEQ: case ISD::SETUEQ:
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| D | R600ISelLowering.cpp | 449 case ISD::SETUEQ: in LowerSELECT_CC()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 571 case ISD::SETUEQ: in getPredicateForSetCC()
618 case ISD::SETUEQ: in getCRIdxForSetCC()
635 case ISD::SETUEQ: in getVCmpInst()
804 case ISD::SETUEQ: in SelectSETCC()
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| D | PPCISelLowering.cpp | 307 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); in PPCTargetLowering()
308 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); in PPCTargetLowering()
490 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand); in PPCTargetLowering()
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUISelLowering.cpp | 301 case ISD::SETUEQ: in LowerMinMax()
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| D | AMDGPUInstructions.td | 42 case ISD::SETOEQ: case ISD::SETUEQ:
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 294 case ISD::SETUEQ: return "setue"; in getOperationName()
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| D | TargetLowering.cpp | 175 case ISD::SETUEQ: in softenSetCCOperands()
1584 if (Cond == ISD::SETUEQ && in SimplifySetCC()
1597 if (Cond == ISD::SETUEQ && in SimplifySetCC()
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| D | SelectionDAG.cpp | 310 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE in getSetCCAndOperation()
1574 case ISD::SETUEQ: in FoldSetCC()
1634 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered || in FoldSetCC()
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| D | LegalizeDAG.cpp | 1633 case ISD::SETUEQ: in LegalizeSetCCCondCode()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1121 setCondCodeAction(ISD::SETUEQ, MVT::f32, Legal); in HexagonTargetLowering()
1122 setCondCodeAction(ISD::SETUEQ, MVT::f64, Legal); in HexagonTargetLowering()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 499 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
843 (setcc node:$lhs, node:$rhs, SETUEQ)>;
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 1702 case ISD::SETUEQ: CondCode = A64CC::EQ; Alternative = A64CC::VS; break; in FPCCToA64CC()
2460 case ISD::SETUEQ: in LowerVectorSETCC()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1235 case ISD::SETUEQ: return SPCC::FCC_UE; in FPCondCCodeToFCC()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXVector.td | 968 (setcc node:$lhs, node:$rhs, SETUEQ)>;
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 479 case ISD::SETUEQ: return Mips::FCOND_UEQ; in condCodeToFCC()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1212 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; in FPCCToARMCC()
4037 case ISD::SETUEQ: Invert = true; // Fallthrough in LowerVSETCC()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 3456 case ISD::SETUEQ: in TranslateX86CC()
9629 case ISD::SETUEQ: in translateX86FSETCC()
9691 if (SetCCOpcode == ISD::SETUEQ) { in LowerVSETCC()
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