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Searched refs:SRC1 (Results 1 – 14 of 14) sorted by relevance

/external/bison/lib/
Dbitset.h218 #define bitset_and(DST, SRC1, SRC2) BITSET_AND_ (DST, SRC1, SRC2) argument
221 #define bitset_and_cmp(DST, SRC1, SRC2) BITSET_AND_CMP_ (DST, SRC1, SRC2) argument
224 #define bitset_andn(DST, SRC1, SRC2) BITSET_ANDN_ (DST, SRC1, SRC2) argument
227 #define bitset_andn_cmp(DST, SRC1, SRC2) BITSET_ANDN_CMP_ (DST, SRC1, SRC2) argument
230 #define bitset_or(DST, SRC1, SRC2) BITSET_OR_ (DST, SRC1, SRC2) argument
233 #define bitset_or_cmp(DST, SRC1, SRC2) BITSET_OR_CMP_ (DST, SRC1, SRC2) argument
236 #define bitset_xor(DST, SRC1, SRC2) BITSET_XOR_ (DST, SRC1, SRC2) argument
239 #define bitset_xor_cmp(DST, SRC1, SRC2) BITSET_XOR_CMP_ (DST, SRC1, SRC2) argument
244 #define bitset_and_or(DST, SRC1, SRC2, SRC3) \ argument
245 BITSET_AND_OR_ (DST, SRC1, SRC2, SRC3)
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Dbbitset.h164 #define BITSET_CHECK3_(DST, SRC1, SRC2) \ argument
165 if (!BITSET_COMPATIBLE_ (DST, SRC1) \
168 #define BITSET_CHECK4_(DST, SRC1, SRC2, SRC3) \ argument
169 if (!BITSET_COMPATIBLE_ (DST, SRC1) || !BITSET_COMPATIBLE_ (DST, SRC2) \
230 #define BITSET_AND_(DST, SRC1, SRC2) (SRC1)->b.vtable->and_ (DST, SRC1, SRC2) argument
231 #define BITSET_AND_CMP_(DST, SRC1, SRC2) (SRC1)->b.vtable->and_cmp (DST, SRC1, SRC2) argument
234 #define BITSET_ANDN_(DST, SRC1, SRC2) (SRC1)->b.vtable->andn (DST, SRC1, SRC2) argument
235 #define BITSET_ANDN_CMP_(DST, SRC1, SRC2) (SRC1)->b.vtable->andn_cmp (DST, SRC1, SRC2) argument
238 #define BITSET_OR_(DST, SRC1, SRC2) (SRC1)->b.vtable->or_ (DST, SRC1, SRC2) argument
239 #define BITSET_OR_CMP_(DST, SRC1, SRC2) (SRC1)->b.vtable->or_cmp (DST, SRC1, SRC2) argument
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/external/chromium_org/third_party/mesa/src/src/mesa/x86/
Dx86_xform3.S42 #define SRC1 REGOFF(4, ESI) macro
109 FLD_S( SRC1 ) /* F0 F7 F6 F5 F4 */
111 FLD_S( SRC1 ) /* F1 F0 F7 F6 F5 F4 */
113 FLD_S( SRC1 ) /* F2 F1 F0 F7 F6 F5 F4 */
115 FLD_S( SRC1 ) /* F3 F2 F1 F0 F7 F6 F5 F4 */
211 FLD_S( SRC1 ) /* F5 F4 */
295 FLD_S( SRC1 ) /* F0 F6 F5 F4 */
297 FLD_S( SRC1 ) /* F1 F0 F6 F5 F4 */
299 FLD_S( SRC1 ) /* F2 F1 F0 F6 F5 F4 */
386 FLD_S( SRC1 ) /* F1 F4 */
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Dx86_xform2.S42 #define SRC1 REGOFF(4, ESI) macro
109 FLD_S( SRC1 ) /* F0 F7 F6 F5 F4 */
111 FLD_S( SRC1 ) /* F1 F0 F7 F6 F5 F4 */
113 FLD_S( SRC1 ) /* F2 F1 F0 F7 F6 F5 F4 */
115 FLD_S( SRC1 ) /* F3 F2 F1 F0 F7 F6 F5 F4 */
197 FLD_S( SRC1 ) /* F1 F4 */
264 FLD_S( SRC1 ) /* F0 F6 F5 F4 */
266 FLD_S( SRC1 ) /* F1 F0 F6 F5 F4 */
268 FLD_S( SRC1 ) /* F2 F1 F0 F6 F5 F4 */
345 FLD_S( SRC1 ) /* F1 F4 */
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Dx86_xform4.S42 #define SRC1 REGOFF(4, ESI) macro
109 FLD_S( SRC1 ) /* F0 F7 F6 F5 F4 */
111 FLD_S( SRC1 ) /* F1 F0 F7 F6 F5 F4 */
113 FLD_S( SRC1 ) /* F2 F1 F0 F7 F6 F5 F4 */
115 FLD_S( SRC1 ) /* F3 F2 F1 F0 F7 F6 F5 F4 */
218 FLD_S( SRC1 ) /* F5 F4 */
305 FLD_S( SRC1 ) /* F0 F6 F5 F4 */
307 FLD_S( SRC1 ) /* F1 F0 F6 F5 F4 */
309 FLD_S( SRC1 ) /* F2 F1 F0 F6 F5 F4 */
404 FLD_S( SRC1 ) /* F5 F4 */
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Dx86_cliptest.S37 #define SRC1 REGOFF(4, ESI) macro
181 MOV_L( SRC1, EBX )
230 FLD_S( SRC1 ) /* F1 F0 F3 */
347 MOV_L( SRC1, EBX )
/external/mesa3d/src/mesa/x86/
Dx86_xform3.S42 #define SRC1 REGOFF(4, ESI) macro
109 FLD_S( SRC1 ) /* F0 F7 F6 F5 F4 */
111 FLD_S( SRC1 ) /* F1 F0 F7 F6 F5 F4 */
113 FLD_S( SRC1 ) /* F2 F1 F0 F7 F6 F5 F4 */
115 FLD_S( SRC1 ) /* F3 F2 F1 F0 F7 F6 F5 F4 */
211 FLD_S( SRC1 ) /* F5 F4 */
295 FLD_S( SRC1 ) /* F0 F6 F5 F4 */
297 FLD_S( SRC1 ) /* F1 F0 F6 F5 F4 */
299 FLD_S( SRC1 ) /* F2 F1 F0 F6 F5 F4 */
386 FLD_S( SRC1 ) /* F1 F4 */
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Dx86_xform2.S42 #define SRC1 REGOFF(4, ESI) macro
109 FLD_S( SRC1 ) /* F0 F7 F6 F5 F4 */
111 FLD_S( SRC1 ) /* F1 F0 F7 F6 F5 F4 */
113 FLD_S( SRC1 ) /* F2 F1 F0 F7 F6 F5 F4 */
115 FLD_S( SRC1 ) /* F3 F2 F1 F0 F7 F6 F5 F4 */
197 FLD_S( SRC1 ) /* F1 F4 */
264 FLD_S( SRC1 ) /* F0 F6 F5 F4 */
266 FLD_S( SRC1 ) /* F1 F0 F6 F5 F4 */
268 FLD_S( SRC1 ) /* F2 F1 F0 F6 F5 F4 */
345 FLD_S( SRC1 ) /* F1 F4 */
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Dx86_xform4.S42 #define SRC1 REGOFF(4, ESI) macro
109 FLD_S( SRC1 ) /* F0 F7 F6 F5 F4 */
111 FLD_S( SRC1 ) /* F1 F0 F7 F6 F5 F4 */
113 FLD_S( SRC1 ) /* F2 F1 F0 F7 F6 F5 F4 */
115 FLD_S( SRC1 ) /* F3 F2 F1 F0 F7 F6 F5 F4 */
218 FLD_S( SRC1 ) /* F5 F4 */
305 FLD_S( SRC1 ) /* F0 F6 F5 F4 */
307 FLD_S( SRC1 ) /* F1 F0 F6 F5 F4 */
309 FLD_S( SRC1 ) /* F2 F1 F0 F6 F5 F4 */
404 FLD_S( SRC1 ) /* F5 F4 */
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Dx86_cliptest.S37 #define SRC1 REGOFF(4, ESI) macro
181 MOV_L( SRC1, EBX )
230 FLD_S( SRC1 ) /* F1 F0 F3 */
347 MOV_L( SRC1, EBX )
/external/mesa3d/src/gallium/drivers/radeon/
DSIInstrInfo.td406 bits<9> SRC1;
419 let Inst{49-41} = SRC1;
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
DSIInstrInfo.td406 bits<9> SRC1;
419 let Inst{49-41} = SRC1;
/external/llvm/lib/Target/R600/
DSIInstructions.td1505 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */),
1511 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */),
1517 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */),
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td139 // Combines the two integer registers SRC1 and SRC2 into a double register.
160 // Combines the two immediates SRC1 and SRC2 into a double register.