| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 490 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
494 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
498 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
502 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
507 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
511 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
515 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
519 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
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| /external/llvm/lib/Target/R600/ |
| D | AMDILISelLowering.cpp | 108 setOperationAction(ISD::SREM, VT, Expand); in InitAMDILLowering()
163 setOperationAction(ISD::SREM, MVT::v2i64, Expand); in InitAMDILLowering()
555 LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS); in LowerSREM8()
572 LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS); in LowerSREM16()
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| D | AMDGPUISelLowering.cpp | 181 case ISD::SREM: return LowerSREM(Op, DAG); in LowerOperation()
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 119 setOperationAction(ISD::SREM, VT, Expand); in InitAMDILLowering()
179 setOperationAction(ISD::SREM, MVT::v2i64, Expand); in InitAMDILLowering()
655 LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS); in LowerSREM8()
673 LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS); in LowerSREM16()
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| D | AMDGPUISelLowering.cpp | 90 case ISD::SREM: return LowerSREM(Op, DAG); in LowerOperation()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 119 setOperationAction(ISD::SREM, VT, Expand); in InitAMDILLowering()
179 setOperationAction(ISD::SREM, MVT::v2i64, Expand); in InitAMDILLowering()
655 LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS); in LowerSREM8()
673 LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS); in LowerSREM16()
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| D | AMDGPUISelLowering.cpp | 90 case ISD::SREM: return LowerSREM(Op, DAG); in LowerOperation()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 176 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1084 setOperationAction(ISD::SREM, MVT::i32, Expand); in HexagonTargetLowering()
1089 setOperationAction(ISD::SREM, MVT::i64, Expand); in HexagonTargetLowering()
1286 setOperationAction(ISD::SREM, MVT::i32, Expand); in HexagonTargetLowering()
1319 setOperationAction(ISD::SREM, MVT::i32, Expand); in HexagonTargetLowering()
1322 setOperationAction(ISD::SREM, MVT::i64, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.h | 479 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); } in visitSRem()
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| D | SelectionDAGDumper.cpp | 159 case ISD::SREM: return "srem"; in getOperationName()
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| D | LegalizeVectorOps.cpp | 198 case ISD::SREM: in LegalizeOp()
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| D | LegalizeVectorTypes.cpp | 108 case ISD::SREM: in ScalarizeVectorResult()
571 case ISD::SREM: in SplitVectorResult()
1464 case ISD::SREM: in WidenVectorResult()
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| D | SelectionDAG.cpp | 2052 case ISD::SREM: in ComputeMaskedBits()
2754 case ISD::SREM: in FoldConstantArithmetic()
2856 case ISD::SREM: in getNode()
3178 case ISD::SREM: in getNode()
3206 case ISD::SREM: in getNode()
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| D | FastISel.cpp | 1004 return SelectBinaryOp(I, ISD::SREM); in SelectOperator()
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| D | LegalizeDAG.cpp | 2024 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV; in useDivRem()
3295 case ISD::SREM: { in ExpandNode()
3297 bool isSigned = Node->getOpcode() == ISD::SREM; in ExpandNode()
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| D | LegalizeIntegerTypes.cpp | 110 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break; in PromoteIntegerResult()
1125 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; in ExpandIntegerResult()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 772 case ISD::SREM: in canOpTrap()
1204 case SRem: return ISD::SREM; in InstructionOpcodeToISD()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 159 setOperationAction(ISD::SREM, MVT::i8, Expand); in MSP430TargetLowering()
165 setOperationAction(ISD::SREM, MVT::i16, Expand); in MSP430TargetLowering()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 138 setOperationAction(ISD::SREM, MVT::i32, Expand); in AArch64TargetLowering()
139 setOperationAction(ISD::SREM, MVT::i64, Expand); in AArch64TargetLowering()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 326 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 288 setOperationAction(ISD::SREM, MVT::i32, Expand); in MipsTargetLowering()
292 setOperationAction(ISD::SREM, MVT::i64, Expand); in MipsTargetLowering()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1270 setOperationAction(ISD::SREM, MVT::i32, Expand); in SparcTargetLowering()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 110 setOperationAction(ISD::SREM, MVT::i32, Expand); in PPCTargetLowering()
112 setOperationAction(ISD::SREM, MVT::i64, Expand); in PPCTargetLowering()
396 setOperationAction(ISD::SREM, VT, Expand); in PPCTargetLowering()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 114 setOperationAction(ISD::SREM, VT, Expand); in SystemZTargetLowering()
|