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Searched refs:SReg (Results 1 – 8 of 8) sorted by relevance

/external/llvm/lib/CodeGen/
DRegisterScavenging.cpp387 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI); in scavengeRegister() local
390 if (!isAliasUsed(SReg)) { in scavengeRegister()
391 DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n"); in scavengeRegister()
392 return SReg; in scavengeRegister()
408 Scavenged[SI].Reg = SReg; in scavengeRegister()
412 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) { in scavengeRegister()
416 TII->storeRegToStackSlot(*MBB, I, SReg, true, Scavenged[SI].FrameIndex, in scavengeRegister()
424 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, Scavenged[SI].FrameIndex, in scavengeRegister()
437 DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) << in scavengeRegister()
440 return SReg; in scavengeRegister()
/external/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp107 unsigned getDPRLaneFromSPR(unsigned SReg);
122 unsigned getPrefSPRLane(unsigned SReg);
151 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) { in getDPRLaneFromSPR() argument
152 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, in getDPRLaneFromSPR()
160 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) { in getPrefSPRLane() argument
161 if (!TRI->isVirtualRegister(SReg)) in getPrefSPRLane()
162 return getDPRLaneFromSPR(SReg); in getPrefSPRLane()
164 MachineInstr *MI = MRI->getVRegDef(SReg); in getPrefSPRLane()
166 MachineOperand *MO = MI->findRegisterDefOperand(SReg); in getPrefSPRLane()
173 SReg = MI->getOperand(1).getReg(); in getPrefSPRLane()
[all …]
DARMAsmPrinter.cpp233 unsigned SReg = Reg - ARM::S0; in EmitDwarfRegOp() local
234 bool odd = SReg & 0x1; in EmitDwarfRegOp()
235 unsigned Rx = 256 + (SReg >> 1); in EmitDwarfRegOp()
240 OutStreamer.AddComment(Twine(SReg)); in EmitDwarfRegOp()
DARMBaseInstrInfo.cpp3767 unsigned SReg, unsigned &Lane) { in getCorrespondingDRegAndLane() argument
3768 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
3775 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
/external/llvm/include/llvm/CodeGen/
DVirtRegMap.h138 void setIsSplitFromReg(unsigned virtReg, unsigned SReg) { in setIsSplitFromReg() argument
139 Virt2SplitMap[virtReg] = SReg; in setIsSplitFromReg()
/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.cpp651 SReg = MF.getRegInfo().createVirtualRegister(RC); in eliminateFrameIndex() local
656 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) in eliminateFrameIndex()
680 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); in eliminateFrameIndex()
/external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
DMemRegion.h1084 const MemRegion *SReg) in CXXBaseObjectRegion() argument
1085 : TypedValueRegion(SReg, CXXBaseObjectRegionKind), Data(RD, IsVirtual) {} in CXXBaseObjectRegion()
1088 bool IsVirtual, const MemRegion *SReg);
/external/clang/lib/StaticAnalyzer/Core/
DMemRegion.cpp411 const MemRegion *SReg) { in ProfileRegion() argument
414 ID.AddPointer(SReg); in ProfileRegion()