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Searched refs:SSE3 (Results 1 – 25 of 52) sorted by relevance

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/external/llvm/test/CodeGen/X86/
Dhaddsub.ll1 ; RUN: llc < %s -march=x86-64 -mattr=+sse3,-avx | FileCheck %s -check-prefix=SSE3
4 ; SSE3-LABEL: haddpd1:
5 ; SSE3-NOT: vhaddpd
6 ; SSE3: haddpd
16 ; SSE3-LABEL: haddpd2:
17 ; SSE3-NOT: vhaddpd
18 ; SSE3: haddpd
28 ; SSE3-LABEL: haddpd3:
29 ; SSE3-NOT: vhaddpd
30 ; SSE3: haddpd
[all …]
Dvec_splat.ll2 ; RUN: llc < %s -march=x86 -mcpu=pentium4 -mattr=+sse3 | FileCheck %s -check-prefix=SSE3
17 ; SSE3-LABEL: test_v4sf:
18 ; SSE3: pshufd $0
32 ; SSE3-LABEL: test_v2sd:
33 ; SSE3: movddup
Dsse2.ll1 ; Tests for SSE2 and below, without SSE3+.
Dsse3.ll1 ; These are tests for SSE3 codegen.
/external/llvm/test/Analysis/CostModel/X86/
Darith.ll2 …st-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=core2 | FileCheck %s --check-prefix=SSE3
51 ; SSE3: sse3mull
53 ; SSE3: cost of 6 {{.*}} mul
56 ; SSE3: avx2mull
/external/llvm/lib/Target/X86/
DX86Subtarget.h45 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512 enumerator
255 bool hasSSE3() const { return X86SSELevel >= SSE3; } in hasSSE3()
DX86.td47 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
48 "Enable SSE3 instructions",
DX86Subtarget.cpp211 if (ECX & 0x1) { X86SSELevel = SSE3; ToggleFeature(X86::FeatureSSE3); } in AutoDetectSubtargetFeatures()
DX86InstrFormats.td487 // SSE3 Instruction Templates:
489 // S3I - SSE3 instructions with TB and OpSize prefixes.
490 // S3SI - SSE3 instructions with XS prefix.
491 // S3DI - SSE3 instructions with XD prefix.
/external/chromium_org/base/
Dcpu.h24 SSE3, enumerator
Dcpu.cc175 if (has_sse3()) return SSE3; in GetIntelMicroArchitecture()
/external/chromium_org/media/base/simd/
Dconvert_rgb_to_yuv_ssse3.asm9 ; This file uses SSE, SSE2, SSE3, and SSSE3, which are supported by all ATOM
13 CPU SSE, SSE3, SSE3, SSSE3
/external/eigen/Eigen/
DCore173 return "SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2";
175 return "SSE, SSE2, SSE3, SSSE3, SSE4.1";
177 return "SSE, SSE2, SSE3, SSSE3";
179 return "SSE, SSE2, SSE3";
/external/eigen/test/eigen2/
Dtestsuite.cmake184 elseif(EIGEN_EXPLICIT_VECTORIZATION MATCHES SSE3)
191 …GEN_EXPLICIT_VECTORIZATION (${EIGEN_EXPLICIT_VECTORIZATION}), must be: novec, SSE2, SSE3, Altivec")
/external/valgrind/main/docs/internals/
D3_2_BUGSTATUS.txt6 sse3fix = fixed by the SSE3 commits
194 6655/6657 SSE3 feature tests for regtests
424 SSE3 commits: vx1635,1636, v5997
434 sse3fix vx1646 Vfd 106852 x86->IR: fisttp (SSE3)
441 sse3fix vx1646 Vfd 129358 x86->IR: fisttpl (SSE3)
/external/eigen/test/
Dtestsuite.cmake210 elseif(EIGEN_EXPLICIT_VECTORIZATION MATCHES SSE3)
223 …GEN_EXPLICIT_VECTORIZATION (${EIGEN_EXPLICIT_VECTORIZATION}), must be: novec, SSE2, SSE3, Altivec")
/external/libvpx/libvpx/test/
Dsad_test.cc531 INSTANTIATE_TEST_CASE_P(SSE3, SADx4Test, ::testing::Values(
543 INSTANTIATE_TEST_CASE_P(SSE3, SADTest, ::testing::Values(
/external/eigen/cmake/
DEigenTesting.cmake223 message(STATUS "SSE3: ON")
225 message(STATUS "SSE3: Using architecture defaults")
388 set(${VAR} SSE3)
/external/v8/src/
Dv8globals.h434 SSE3 = 32 + 0, // x86 enumerator
/external/chromium_org/v8/src/
Dv8globals.h425 SSE3 = 32 + 0, // x86 enumerator
/external/eigen/
DCMakeLists.txt135 option(EIGEN_TEST_SSE3 "Enable/Disable SSE3 in tests/examples" OFF)
138 message(STATUS "Enabling SSE3 in tests/examples")
/external/clang/lib/Basic/
DTargets.cpp1573 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2 enumerator
2353 .Case("sse3", SSE3) in HandleTargetFeatures()
2581 case SSE3: in getTargetDefines()
2600 case SSE3: in getTargetDefines()
2654 .Case("sse3", SSELevel >= SSE3) in hasFeature()
/external/chromium_org/v8/src/ia32/
Dassembler-ia32.cc109 probed_features |= static_cast<uint64_t>(1) << SSE3; in Probe()
1647 ASSERT(IsEnabled(SSE3)); in fisttp_s()
1655 ASSERT(IsEnabled(SSE3)); in fisttp_d()
/external/v8/src/ia32/
Dcode-stubs-ia32.h164 use_sse3_ = CpuFeatures::IsSupported(SSE3); in BinaryOpStub()
/external/chromium_org/v8/src/x64/
Dassembler-x64.cc72 probed_features |= static_cast<uint64_t>(1) << SSE3; in Probe()
2176 ASSERT(IsEnabled(SSE3)); in fisttp_s()
2185 ASSERT(IsEnabled(SSE3)); in fisttp_d()

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