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Searched refs:STI (Results 1 – 25 of 111) sorted by relevance

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/external/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp36 MipsDisassemblerBase(const MCSubtargetInfo &STI, const MCRegisterInfo *Info, in MipsDisassemblerBase() argument
38 MCDisassembler(STI), RegInfo(Info), isBigEndian(bigEndian) {} in MipsDisassemblerBase()
55 MipsDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info, in MipsDisassembler() argument
57 MipsDisassemblerBase(STI, Info, bigEndian) {} in MipsDisassembler()
74 Mips64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info, in Mips64Disassembler() argument
76 MipsDisassemblerBase(STI, Info, bigEndian) {} in Mips64Disassembler()
197 const MCSubtargetInfo &STI) { in createMipsDisassembler() argument
198 return new MipsDisassembler(STI, T.createMCRegInfo(""), true); in createMipsDisassembler()
203 const MCSubtargetInfo &STI) { in createMipselDisassembler() argument
204 return new MipsDisassembler(STI, T.createMCRegInfo(""), false); in createMipselDisassembler()
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/
DAMDGPUMCTargetDesc.cpp69 const MCSubtargetInfo &STI) { in createAMDGPUMCInstPrinter() argument
74 const MCSubtargetInfo &STI, in createAMDGPUMCCodeEmitter() argument
76 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) { in createAMDGPUMCCodeEmitter()
77 return createSIMCCodeEmitter(MCII, STI, Ctx); in createAMDGPUMCCodeEmitter()
79 return createR600MCCodeEmitter(MCII, STI, Ctx); in createAMDGPUMCCodeEmitter()
DAMDGPUMCTargetDesc.h32 const MCSubtargetInfo &STI,
36 const MCSubtargetInfo &STI,
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
DAMDGPUMCTargetDesc.cpp69 const MCSubtargetInfo &STI) { in createAMDGPUMCInstPrinter() argument
74 const MCSubtargetInfo &STI, in createAMDGPUMCCodeEmitter() argument
76 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) { in createAMDGPUMCCodeEmitter()
77 return createSIMCCodeEmitter(MCII, STI, Ctx); in createAMDGPUMCCodeEmitter()
79 return createR600MCCodeEmitter(MCII, STI, Ctx); in createAMDGPUMCCodeEmitter()
DAMDGPUMCTargetDesc.h32 const MCSubtargetInfo &STI,
36 const MCSubtargetInfo &STI,
/external/llvm/lib/Target/R600/MCTargetDesc/
DAMDGPUMCTargetDesc.cpp70 const MCSubtargetInfo &STI) { in createAMDGPUMCInstPrinter() argument
76 const MCSubtargetInfo &STI, in createAMDGPUMCCodeEmitter() argument
78 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) { in createAMDGPUMCCodeEmitter()
79 return createSIMCCodeEmitter(MCII, MRI, STI, Ctx); in createAMDGPUMCCodeEmitter()
81 return createR600MCCodeEmitter(MCII, MRI, STI); in createAMDGPUMCCodeEmitter()
DR600MCCodeEmitter.cpp38 const MCSubtargetInfo &STI; member in __anon094eb6db0111::R600MCCodeEmitter
44 : MCII(mcii), MRI(mri), STI(sti) { } in R600MCCodeEmitter()
86 const MCSubtargetInfo &STI) { in createR600MCCodeEmitter() argument
87 return new R600MCCodeEmitter(MCII, MRI, STI); in createR600MCCodeEmitter()
102 if (!(STI.getFeatureBits() & AMDGPU::FeatureCaymanISA)) { in EncodeInstruction()
135 if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) && in EncodeInstruction()
DAMDGPUMCTargetDesc.h36 const MCSubtargetInfo &STI);
40 const MCSubtargetInfo &STI,
/external/llvm/include/llvm/MC/
DMCDisassembler.h59 MCDisassembler(const MCSubtargetInfo &STI) : GetOpInfo(0), SymbolLookUp(0), in MCDisassembler() argument
61 STI(STI), Symbolizer(0), in MCDisassembler()
104 const MCSubtargetInfo &STI;
/external/llvm/lib/MC/MCDisassembler/
DDisassembler.cpp64 const MCSubtargetInfo *STI = TheTarget->createMCSubtargetInfo(Triple, CPU, in LLVMCreateDisasmCPU() local
66 if (!STI) in LLVMCreateDisasmCPU()
75 MCDisassembler *DisAsm = TheTarget->createMCDisassembler(*STI); in LLVMCreateDisasmCPU()
93 *MAI, *MII, *MRI, *STI); in LLVMCreateDisasmCPU()
100 STI, MII, Ctx, DisAsm, IP); in LLVMCreateDisasmCPU()
225 const MCSubtargetInfo *STI = DC->getSubtargetInfo(); in LLVMSetDisasmOptions() local
229 AsmPrinterVariant, *MAI, *MII, *MRI, *STI); in LLVMSetDisasmOptions()
/external/llvm/lib/CodeGen/
DTargetSchedule.cpp58 STI = sti; in init()
60 STI->initInstrItins(InstrItins); in init()
117 SchedClass = STI->resolveSchedClass(SchedClass, MI, this); in resolveSchedClass()
193 STI->getWriteLatencyEntry(SCDesc, DefIdx); in computeOperandLatency()
204 int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID); in computeOperandLatency()
241 STI->getWriteLatencyEntry(SCDesc, DefIdx); in computeInstrLatency()
276 for (const MCWriteProcResEntry *PRI = STI->getWriteProcResBegin(SCDesc), in computeOutputLatency()
277 *PRE = STI->getWriteProcResEnd(SCDesc); PRI != PRE; ++PRI) { in computeOutputLatency()
DLLVMTargetMachine.cpp167 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>(); in addPassesToEmitFile() local
174 MII, MRI, STI); in addPassesToEmitFile()
180 MCE = getTarget().createMCCodeEmitter(MII, MRI, STI, *Context); in addPassesToEmitFile()
198 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, STI, in addPassesToEmitFile()
271 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>(); in addPassesToEmitMC() local
273 STI, *Ctx); in addPassesToEmitMC()
/external/llvm/include/llvm/CodeGen/
DTargetSchedule.h37 const TargetSubtargetInfo *STI; variable
44 TargetSchedModel(): STI(0), TII(0) {} in TargetSchedModel()
107 return STI->getWriteProcResBegin(SC); in getWriteProcResBegin()
110 return STI->getWriteProcResEnd(SC); in getWriteProcResEnd()
/external/llvm/lib/Target/Mips/
DMipsSEFrameLowering.h23 explicit MipsSEFrameLowering(const MipsSubtarget &STI) in MipsSEFrameLowering() argument
24 : MipsFrameLowering(STI, STI.hasMips64() ? 16 : 8) {} in MipsSEFrameLowering()
DMipsSEFrameLowering.cpp261 return STI.isABI_N64() ? EhDataReg64[I] : EhDataReg[I]; in ehDataReg()
276 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; in emitPrologue()
277 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; in emitPrologue()
278 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; in emitPrologue()
279 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; in emitPrologue()
328 if (!STI.isLittle()) in emitPrologue()
344 const TargetRegisterClass *RC = STI.isABI_N64() ? in emitPrologue()
392 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; in emitEpilogue()
393 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; in emitEpilogue()
394 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; in emitEpilogue()
[all …]
DMipsSEInstrInfo.cpp317 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>(); in adjustStackPtr() local
319 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; in adjustStackPtr()
320 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; in adjustStackPtr()
337 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>(); in loadImmediate() local
339 unsigned Size = STI.isABI_N64() ? 64 : 32; in loadImmediate()
340 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi; in loadImmediate()
341 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; in loadImmediate()
342 const TargetRegisterClass *RC = STI.isABI_N64() ? in loadImmediate()
512 const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>(); in expandEhReturn() local
513 unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; in expandEhReturn()
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DMipsFrameLowering.h26 const MipsSubtarget &STI;
30 : TargetFrameLowering(StackGrowsDown, Alignment, 0, Alignment), STI(sti) {} in MipsFrameLowering()
DMips16FrameLowering.h22 explicit Mips16FrameLowering(const MipsSubtarget &STI) in Mips16FrameLowering() argument
23 : MipsFrameLowering(STI, 8) {} in Mips16FrameLowering()
/external/llvm/lib/Target/ARM/
DARMBaseRegisterInfo.cpp47 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), STI(sti), in ARMBaseRegisterInfo()
48 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), in ARMBaseRegisterInfo()
66 return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) in getCalleeSavedRegs()
75 return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) in getCallPreservedMask()
97 return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) in getThisReturnPreservedMask()
116 if (STI.isR9Reserved()) in getReservedRegs()
119 if (!STI.hasVFP3() || STI.hasD16()) { in getReservedRegs()
178 return 10 - FP - (STI.isR9Reserved() ? 1 : 0); in getRegPressureLimit()
268 if (!STI.isLikeA9()) in avoidWriteAfterWrite()
/external/llvm/include/llvm/Support/
DTargetRegistry.h109 typedef MCTargetAsmParser *(*MCAsmParserCtorTy)(MCSubtargetInfo &STI,
112 const MCSubtargetInfo &STI);
118 const MCSubtargetInfo &STI);
121 const MCSubtargetInfo &STI,
386 MCTargetAsmParser *createMCAsmParser(MCSubtargetInfo &STI, in createMCAsmParser() argument
390 return MCAsmParserCtorFn(STI, Parser); in createMCAsmParser()
401 MCDisassembler *createMCDisassembler(const MCSubtargetInfo &STI) const { in createMCDisassembler() argument
404 return MCDisassemblerCtorFn(*this, STI); in createMCDisassembler()
411 const MCSubtargetInfo &STI) const { in createMCInstPrinter() argument
414 return MCInstPrinterCtorFn(*this, SyntaxVariant, MAI, MII, MRI, STI); in createMCInstPrinter()
[all …]
/external/llvm/lib/Target/X86/
DX86FrameLowering.cpp491 bool Is64Bit = STI.is64Bit(); in getCompactUnwindEncoding()
659 bool Is64Bit = STI.is64Bit(); in emitPrologue()
660 bool IsLP64 = STI.isTarget64BitLP64(); in emitPrologue()
661 bool IsWin64 = STI.isTargetWin64(); in emitPrologue()
662 bool UseLEA = STI.useLeaForSP(); in emitPrologue()
866 if (NumBytes >= 4096 && STI.isTargetCOFF() && !STI.isTargetEnvMacho()) { in emitPrologue()
871 if (STI.isTargetCygMing()) in emitPrologue()
877 } else if (STI.isTargetCygMing()) in emitPrologue()
969 if (STI.getTargetTriple().isMacOSX() && in emitPrologue()
970 !STI.getTargetTriple().isMacOSXVersionLT(10, 7)) in emitPrologue()
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/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsMCCodeEmitter.cpp40 const MCSubtargetInfo &STI; member in __anon3852d87d0111::MipsMCCodeEmitter
46 MCII(mcii), Ctx(Ctx_), STI (sti), IsLittleEndian(IsLittle) {} in MipsMCCodeEmitter()
102 const MCSubtargetInfo &STI, in createMipsMCCodeEmitterEB() argument
105 return new MipsMCCodeEmitter(MCII, Ctx, STI, false); in createMipsMCCodeEmitterEB()
110 const MCSubtargetInfo &STI, in createMipsMCCodeEmitterEL() argument
113 return new MipsMCCodeEmitter(MCII, Ctx, STI, true); in createMipsMCCodeEmitterEL()
213 if (STI.getFeatureBits() & Mips::FeatureMicroMips) { in EncodeInstruction()
/external/llvm/tools/llvm-mc/
Dllvm-mc.cpp322 MCAsmInfo &MAI, MCSubtargetInfo &STI) { in AssembleInput() argument
325 OwningPtr<MCTargetAsmParser> TAP(TheTarget->createMCAsmParser(STI, *Parser)); in AssembleInput()
425 STI(TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr)); in main() local
430 TheTarget->createMCInstPrinter(OutputAsmVariant, *MAI, *MCII, *MRI, *STI); in main()
434 CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, *STI, Ctx); in main()
448 MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, *STI, Ctx); in main()
462 Res = AssembleInput(ProgName, TheTarget, SrcMgr, Ctx, *Str, *MAI, *STI); in main()
479 Res = Disassembler::disassemble(*TheTarget, TripleName, *STI, *Str, in main()
/external/llvm/lib/Target/Hexagon/
DHexagonFrameLowering.h21 const HexagonSubtarget &STI;
26 : TargetFrameLowering(StackGrowsDown, 8, 0), STI(sti) { in HexagonFrameLowering()
/external/llvm/lib/Target/MSP430/
DMSP430FrameLowering.h26 const MSP430Subtarget &STI;
30 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 2, -2), STI(sti) { in MSP430FrameLowering()

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