| /external/llvm/lib/Target/Mips/ |
| D | Mips16ISelDAGToDAG.cpp | 252 case ISD::SUBE: in selectNode()
257 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && in selectNode()
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| D | MipsSEISelDAGToDAG.cpp | 222 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && in selectAddESubE()
330 case ISD::SUBE: { in selectNode()
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| D | MipsSEISelLowering.cpp | 115 setTargetDAGCombine(ISD::SUBE); in MipsSETargetLowering()
499 case ISD::SUBE: in PerformDAGCombine()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 204 ADDE, SUBE, enumerator
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1390 setOperationAction(ISD::SUBE, MVT::i8, Expand); in HexagonTargetLowering()
1391 setOperationAction(ISD::SUBE, MVT::i16, Expand); in HexagonTargetLowering()
1392 setOperationAction(ISD::SUBE, MVT::i32, Expand); in HexagonTargetLowering()
1393 setOperationAction(ISD::SUBE, MVT::i64, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 83 SUBE, // Sub using carry enumerator
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| D | ARMISelLowering.cpp | 670 setOperationAction(ISD::SUBE, MVT::i32, Custom); in ARMTargetLowering()
998 case ARMISD::SUBE: return "ARMISD::SUBE"; in getTargetNodeName()
5762 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break; in LowerADDC_ADDE_SUBC_SUBE()
5904 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); in LowerOperation()
10417 case ARMISD::SUBE: in computeMaskedBitsForTargetNode()
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| D | ARMInstrInfo.td | 155 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 205 case ISD::SUBE: return "sube"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 1161 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; in ExpandIntegerResult()
1553 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); in ExpandIntRes_ADDSUB()
1602 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); in ExpandIntRes_ADDSUBC()
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| D | DAGCombiner.cpp | 1113 case ISD::SUBE: return visitSUBE(N); in visit()
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| /external/llvm/lib/Target/R600/ |
| D | AMDILISelLowering.cpp | 100 setOperationAction(ISD::SUBE, VT, Expand); in InitAMDILLowering()
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 111 setOperationAction(ISD::SUBE, VT, Expand); in InitAMDILLowering()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 111 setOperationAction(ISD::SUBE, VT, Expand); in InitAMDILLowering()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 347 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 94 setOperationAction(ISD::SUBE, MVT::i32, Expand); in XCoreTargetLowering()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 429 setOperationAction(ISD::SUBE, VT, Custom); in resetOperationActions()
12735 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; in LowerADDC_ADDE_SUBC_SUBE()
12873 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); in LowerOperation()
12939 case ISD::SUBE: in ReplaceNodeResults()
|