Searched refs:SXTB (Results 1 – 17 of 17) sorted by relevance
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 503 # SXTB/SXTH
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| D | invalid-armv7.txt | 338 # A8.6.223 SXTB
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| D | thumb2.txt | 2157 # SXTB
2211 # SXTB
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| D | basic-arm-instructions.txt | 1991 # SXTB
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 350 case A64SE::SXTB: O << "sxtb"; break; in printRegExtendOperand()
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| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 302 SXTB, enumerator
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| /external/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 615 @ SXTB/SXTH
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| D | basic-thumb2-instructions.s | 2952 @ SXTB
3010 @ SXTB
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| D | basic-arm-instructions.s | 2496 @ SXTB
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.td | 469 defm SXTB : ALU32_2op_base<"sxtb">, PredNewRel;
481 (SXTB IntRegs:$src1)>;
2224 // Map from Rdd = sign_extend_inreg(Rss, i8) -> Rdd = SXTW(SXTB(Rss.lo)).
2226 (i64 (SXTW (i32 (SXTB (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
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| D | HexagonInstrInfo.cpp | 713 case Hexagon::SXTB: in isPredicable()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 2665 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2909 { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 },
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| D | ARMScheduleSwift.td | 1194 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
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| D | ARMInstrInfo.td | 3099 def SXTB : AI_ext_rrot<0b01101010,
5097 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5200 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
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| D | ARMISelLowering.cpp | 6221 extendOpc = isThumb2 ? ARM::t2SXTB : ARM::SXTB; in EmitAtomicBinaryMinMax()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1772 .Case("sxtb", A64SE::SXTB) in ParseShiftExtend()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 265 defm SXTB : extend_operands<"SXTB", "Small">;
1073 // instruction alias: their syntax is (for example) "SXTB x0, w0", which needs
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