Searched refs:SXTH (Results 1 – 17 of 17) sorted by relevance
/external/llvm/test/MC/Disassembler/ARM/ |
D | thumb1.txt | 503 # SXTB/SXTH
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D | thumb2.txt | 2193 # SXTH 2247 # SXTH
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D | basic-arm-instructions.txt | 2023 # SXTH
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/external/llvm/lib/Target/AArch64/InstPrinter/ |
D | AArch64InstPrinter.cpp | 351 case A64SE::SXTH: O << "sxth"; break; in printRegExtendOperand()
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/external/llvm/lib/Target/AArch64/Utils/ |
D | AArch64BaseInfo.h | 303 SXTH, enumerator
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/external/llvm/test/MC/ARM/ |
D | basic-thumb-instructions.s | 615 @ SXTB/SXTH
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D | basic-thumb2-instructions.s | 2990 @ SXTH 3046 @ SXTH
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D | basic-arm-instructions.s | 2528 @ SXTH
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonISelDAGToDAG.cpp | 936 SDNode *SextNode = CurDAG->getMachineNode(Hexagon::SXTH, dl, in SelectSelect() 960 SDNode *SextNode = CurDAG->getMachineNode(Hexagon::SXTH, dl, in SelectSelect()
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D | HexagonInstrInfo.td | 470 defm SXTH : ALU32_2op_base<"sxth">, PredNewRel; 484 (SXTH IntRegs:$src1)>; 2219 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)). 2221 (i64 (SXTW (i32 (SXTH (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
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D | HexagonInstrInfo.cpp | 714 case Hexagon::SXTH: in isPredicable()
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/external/llvm/lib/Target/ARM/ |
D | ARMFastISel.cpp | 2667 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt() 2906 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
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D | ARMScheduleSwift.td | 1194 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
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D | ARMInstrInfo.td | 3101 def SXTH : AI_ext_rrot<0b01101011, 5098 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>; 5204 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
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D | ARMISelLowering.cpp | 6226 extendOpc = isThumb2 ? ARM::t2SXTH : ARM::SXTH; in EmitAtomicBinaryMinMax()
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/external/llvm/lib/Target/AArch64/AsmParser/ |
D | AArch64AsmParser.cpp | 1773 .Case("sxth", A64SE::SXTH) in ParseShiftExtend()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64InstrInfo.td | 266 defm SXTH : extend_operands<"SXTH", "Small">;
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