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Searched refs:SXTH (Results 1 – 17 of 17) sorted by relevance

/external/llvm/test/MC/Disassembler/ARM/
Dthumb1.txt503 # SXTB/SXTH
Dthumb2.txt2193 # SXTH
2247 # SXTH
Dbasic-arm-instructions.txt2023 # SXTH
/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp351 case A64SE::SXTH: O << "sxth"; break; in printRegExtendOperand()
/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h303 SXTH, enumerator
/external/llvm/test/MC/ARM/
Dbasic-thumb-instructions.s615 @ SXTB/SXTH
Dbasic-thumb2-instructions.s2990 @ SXTH
3046 @ SXTH
Dbasic-arm-instructions.s2528 @ SXTH
/external/llvm/lib/Target/Hexagon/
DHexagonISelDAGToDAG.cpp936 SDNode *SextNode = CurDAG->getMachineNode(Hexagon::SXTH, dl, in SelectSelect()
960 SDNode *SextNode = CurDAG->getMachineNode(Hexagon::SXTH, dl, in SelectSelect()
DHexagonInstrInfo.td470 defm SXTH : ALU32_2op_base<"sxth">, PredNewRel;
484 (SXTH IntRegs:$src1)>;
2219 // Map from Rdd = sign_extend_inreg(Rss, i16) -> Rdd = SXTW(SXTH(Rss.lo)).
2221 (i64 (SXTW (i32 (SXTH (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
DHexagonInstrInfo.cpp714 case Hexagon::SXTH: in isPredicable()
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp2667 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2906 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
DARMScheduleSwift.td1194 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
DARMInstrInfo.td3101 def SXTH : AI_ext_rrot<0b01101011,
5098 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5204 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
DARMISelLowering.cpp6226 extendOpc = isThumb2 ? ARM::t2SXTH : ARM::SXTH; in EmitAtomicBinaryMinMax()
/external/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp1773 .Case("sxth", A64SE::SXTH) in ParseShiftExtend()
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td266 defm SXTH : extend_operands<"SXTH", "Small">;