| /external/icu4c/layout/ |
| D | LigatureSubstProc.cpp | 20 #define SignBit(m) ((ExtendedComplement(m) >> 1) & (le_int32)(m)) macro
21 #define SignExtend(v,m) (((v) & SignBit(m))? ((v) | ExtendedComplement(m)): (v))
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| D | LigatureSubstProc2.cpp | 20 #define SignBit(m) ((ExtendedComplement(m) >> 1) & (le_int32)(m)) macro
21 #define SignExtend(v,m) (((v) & SignBit(m))? ((v) | ExtendedComplement(m)): (v))
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeFloatTypes.cpp | 190 SDValue SignBit = DAG.getNode(ISD::SHL, dl, RVT, DAG.getConstant(1, RVT), in SoftenFloatRes_FCOPYSIGN() local
193 SignBit = DAG.getNode(ISD::AND, dl, RVT, RHS, SignBit); in SoftenFloatRes_FCOPYSIGN()
198 SignBit = DAG.getNode(ISD::SRL, dl, RVT, SignBit, in SoftenFloatRes_FCOPYSIGN()
200 TLI.getShiftAmountTy(SignBit.getValueType()))); in SoftenFloatRes_FCOPYSIGN()
201 SignBit = DAG.getNode(ISD::TRUNCATE, dl, LVT, SignBit); in SoftenFloatRes_FCOPYSIGN()
203 SignBit = DAG.getNode(ISD::ANY_EXTEND, dl, LVT, SignBit); in SoftenFloatRes_FCOPYSIGN()
204 SignBit = DAG.getNode(ISD::SHL, dl, LVT, SignBit, in SoftenFloatRes_FCOPYSIGN()
206 TLI.getShiftAmountTy(SignBit.getValueType()))); in SoftenFloatRes_FCOPYSIGN()
217 return DAG.getNode(ISD::OR, dl, LVT, LHS, SignBit); in SoftenFloatRes_FCOPYSIGN()
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| D | LegalizeDAG.cpp | 1507 SDValue SignBit; in ExpandFCOPYSIGN() local
1512 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2); in ExpandFCOPYSIGN()
1525 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(), in ExpandFCOPYSIGN()
1536 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(), in ExpandFCOPYSIGN()
1543 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit, in ExpandFCOPYSIGN()
1545 TLI.getShiftAmountTy(SignBit.getValueType()))); in ExpandFCOPYSIGN()
1549 SignBit = DAG.getSetCC(dl, getSetCCResultType(SignBit.getValueType()), in ExpandFCOPYSIGN()
1550 SignBit, DAG.getConstant(0, SignBit.getValueType()), in ExpandFCOPYSIGN()
1556 return DAG.getSelect(dl, AbsVal.getValueType(), SignBit, in ExpandFCOPYSIGN()
2247 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); in ExpandLegalINT_TO_FP() local
[all …]
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| D | TargetLowering.cpp | 721 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); in SimplifyDemandedBits() local
725 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { in SimplifyDemandedBits()
729 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. in SimplifyDemandedBits()
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| D | SelectionDAG.cpp | 1862 APInt SignBit = APInt::getSignBit(BitWidth); in ComputeMaskedBits() local
1863 SignBit = SignBit.lshr(ShAmt); // Adjust to where it is now in the mask. in ComputeMaskedBits()
1865 if (KnownZero.intersects(SignBit)) { in ComputeMaskedBits()
1867 } else if (KnownOne.intersects(SignBit)) { in ComputeMaskedBits()
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| D | DAGCombiner.cpp | 5691 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); in visitBITCAST() local
5694 NewConv, DAG.getConstant(SignBit, VT)); in visitBITCAST()
5697 NewConv, DAG.getConstant(~SignBit, VT)); in visitBITCAST()
5730 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); in visitBITCAST() local
5732 X, DAG.getConstant(SignBit, VT)); in visitBITCAST()
5738 Cst, DAG.getConstant(~SignBit, VT)); in visitBITCAST()
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| /external/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineSimplifyDemanded.cpp | 697 APInt SignBit(APInt::getSignBit(BitWidth)); in SimplifyDemandedUseBits() local
699 SignBit = APIntOps::lshr(SignBit, ShiftAmt); in SimplifyDemandedUseBits()
710 } else if ((KnownOne & SignBit) != 0) { // New bits are known one. in SimplifyDemandedUseBits()
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| D | InstCombineCompares.cpp | 1110 const APInt &SignBit = XorCST->getValue(); in visitICmpInstWithInstAndIntCst() local
1115 Builder->getInt(RHSV ^ SignBit)); in visitICmpInstWithInstAndIntCst()
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| /external/llvm/lib/Support/ |
| D | APInt.cpp | 1049 unsigned SignBit = APINT_BITS_PER_WORD - BitWidth; in ashr() local
1051 (((int64_t(VAL) << SignBit) >> SignBit) >> shiftAmt)); in ashr()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 9119 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); in LowerFCOPYSIGN() local
9124 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); in LowerFCOPYSIGN()
9125 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, in LowerFCOPYSIGN()
9127 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); in LowerFCOPYSIGN()
9128 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, in LowerFCOPYSIGN()
9155 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); in LowerFCOPYSIGN()
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