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Searched refs:X86 (Results 1 – 25 of 212) sorted by relevance

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/external/llvm/lib/Target/X86/
DX86InstrInfo.cpp95 ? X86::ADJCALLSTACKDOWN64 in X86InstrInfo()
96 : X86::ADJCALLSTACKDOWN32), in X86InstrInfo()
98 ? X86::ADJCALLSTACKUP64 in X86InstrInfo()
99 : X86::ADJCALLSTACKUP32)), in X86InstrInfo()
103 { X86::ADC32ri, X86::ADC32mi, 0 }, in X86InstrInfo()
104 { X86::ADC32ri8, X86::ADC32mi8, 0 }, in X86InstrInfo()
105 { X86::ADC32rr, X86::ADC32mr, 0 }, in X86InstrInfo()
106 { X86::ADC64ri32, X86::ADC64mi32, 0 }, in X86InstrInfo()
107 { X86::ADC64ri8, X86::ADC64mi8, 0 }, in X86InstrInfo()
108 { X86::ADC64rr, X86::ADC64mr, 0 }, in X86InstrInfo()
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DX86RegisterInfo.cpp59 ? X86::RIP : X86::EIP), in X86RegisterInfo()
63 ? X86::RIP : X86::EIP)), in X86RegisterInfo()
74 StackPtr = X86::RSP; in X86RegisterInfo()
75 FramePtr = X86::RBP; in X86RegisterInfo()
78 StackPtr = X86::ESP; in X86RegisterInfo()
79 FramePtr = X86::EBP; in X86RegisterInfo()
84 BasePtr = Is64Bit ? X86::RBX : X86::ESI; in X86RegisterInfo()
91 case X86::EBX: case X86::RBX: return 1; in getCompactUnwindRegNum()
92 case X86::ECX: case X86::R12: return 2; in getCompactUnwindRegNum()
93 case X86::EDX: case X86::R13: return 3; in getCompactUnwindRegNum()
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DX86FloatingPoint.cpp119 if (Reg < X86::FP0 || Reg > X86::FP6) in calcLiveInMask()
121 Mask |= 1 << (Reg - X86::FP0); in calcLiveInMask()
224 return StackTop - 1 - getSlot(RegNo) + X86::ST0; in getSTReg()
253 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); in moveToTop()
262 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg); in duplicateToTop()
319 return X86::RFP80RegClass.contains(DstReg) || in isFPCopy()
320 X86::RFP80RegClass.contains(SrcReg); in isFPCopy()
333 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); in getFPReg()
334 return Reg - X86::FP0; in getFPReg()
345 assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!"); in runOnMachineFunction()
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DX86MCInstLower.cpp247 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortImmForm()
265 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw in SimplifyMOVSX()
266 if (Op0 == X86::AX && Op1 == X86::AL) in SimplifyMOVSX()
267 NewOpcode = X86::CBW; in SimplifyMOVSX()
269 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl in SimplifyMOVSX()
270 if (Op0 == X86::EAX && Op1 == X86::AX) in SimplifyMOVSX()
271 NewOpcode = X86::CWDE; in SimplifyMOVSX()
273 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq in SimplifyMOVSX()
274 if (Op0 == X86::RAX && Op1 == X86::EAX) in SimplifyMOVSX()
275 NewOpcode = X86::CDQE; in SimplifyMOVSX()
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DX86FrameLowering.cpp61 return X86::SUB64ri8; in getSUBriOpcode()
62 return X86::SUB64ri32; in getSUBriOpcode()
65 return X86::SUB32ri8; in getSUBriOpcode()
66 return X86::SUB32ri; in getSUBriOpcode()
73 return X86::ADD64ri8; in getADDriOpcode()
74 return X86::ADD64ri32; in getADDriOpcode()
77 return X86::ADD32ri8; in getADDriOpcode()
78 return X86::ADD32ri; in getADDriOpcode()
83 return IsLP64 ? X86::LEA64r : X86::LEA32r; in getLEArOpcode()
99 X86::EAX, X86::EDX, X86::ECX, 0 in findDeadCallerSavedReg()
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DX86FastISel.cpp188 Opc = X86::MOV8rm; in X86FastEmitLoad()
189 RC = &X86::GR8RegClass; in X86FastEmitLoad()
192 Opc = X86::MOV16rm; in X86FastEmitLoad()
193 RC = &X86::GR16RegClass; in X86FastEmitLoad()
196 Opc = X86::MOV32rm; in X86FastEmitLoad()
197 RC = &X86::GR32RegClass; in X86FastEmitLoad()
201 Opc = X86::MOV64rm; in X86FastEmitLoad()
202 RC = &X86::GR64RegClass; in X86FastEmitLoad()
206 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm; in X86FastEmitLoad()
207 RC = &X86::FR32RegClass; in X86FastEmitLoad()
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DX86ISelDAGToDAG.cpp91 return RegNode->getReg() == X86::RIP; in isRIPRelative()
562 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32; in EmitSpecialCodeForMain()
590 if (!X86::isOffsetSuitableForCodeModel(Val, M, in FoldOffsetIntoAddress()
618 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16); in MatchLoadInAddress()
621 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16); in MatchLoadInAddress()
686 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64)); in MatchWrapper()
751 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64); in MatchAddress()
1318 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16); in SelectAddr()
1320 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16); in SelectAddr()
1429 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)), in SelectLEA64_32Addr()
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DX86Subtarget.cpp207 if ((EDX >> 15) & 1) { HasCMov = true; ToggleFeature(X86::FeatureCMOV); } in AutoDetectSubtargetFeatures()
208 if ((EDX >> 23) & 1) { X86SSELevel = MMX; ToggleFeature(X86::FeatureMMX); } in AutoDetectSubtargetFeatures()
209 if ((EDX >> 25) & 1) { X86SSELevel = SSE1; ToggleFeature(X86::FeatureSSE1); } in AutoDetectSubtargetFeatures()
210 if ((EDX >> 26) & 1) { X86SSELevel = SSE2; ToggleFeature(X86::FeatureSSE2); } in AutoDetectSubtargetFeatures()
211 if (ECX & 0x1) { X86SSELevel = SSE3; ToggleFeature(X86::FeatureSSE3); } in AutoDetectSubtargetFeatures()
212 if ((ECX >> 9) & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);} in AutoDetectSubtargetFeatures()
213 if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);} in AutoDetectSubtargetFeatures()
214 if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);} in AutoDetectSubtargetFeatures()
216 X86SSELevel = AVX; ToggleFeature(X86::FeatureAVX); in AutoDetectSubtargetFeatures()
224 ToggleFeature(X86::FeaturePCLMUL); in AutoDetectSubtargetFeatures()
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DX86CodeEmitter.cpp149 if (Desc.getOpcode() == X86::MOVPC32r) in runOnMachineFunction()
150 emitInstruction(*I, &II->get(X86::POP32r)); in runOnMachineFunction()
224 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands); in determineREX()
265 X86::reloc_pcrel_word, MBB)); in emitPCRelativeBlockAddress()
279 if (Reloc == X86::reloc_picrel_word) in emitGlobalAddress()
281 else if (Reloc == X86::reloc_pcrel_word) in emitGlobalAddress()
291 if (Reloc == X86::reloc_absolute_dword) in emitGlobalAddress()
303 intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0; in emitExternalSymbolAddress()
313 if (Reloc == X86::reloc_absolute_dword) in emitExternalSymbolAddress()
327 if (Reloc == X86::reloc_picrel_word) in emitConstPoolAddress()
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DX86FixupLEAs.cpp100 case X86::MOV32rr: in postRAConvertToLEA()
101 case X86::MOV64rr: { in postRAConvertToLEA()
105 TII->get( MI->getOpcode() == X86::MOV32rr ? X86::LEA32r : X86::LEA64r)) in postRAConvertToLEA()
111 case X86::ADD64ri32: in postRAConvertToLEA()
112 case X86::ADD64ri8: in postRAConvertToLEA()
113 case X86::ADD64ri32_DB: in postRAConvertToLEA()
114 case X86::ADD64ri8_DB: in postRAConvertToLEA()
115 case X86::ADD32ri: in postRAConvertToLEA()
116 case X86::ADD32ri8: in postRAConvertToLEA()
117 case X86::ADD32ri_DB: in postRAConvertToLEA()
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DX86RegisterInfo.td1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
10 // This file describes the X86 Register file, defining the registers themselves,
17 let Namespace = "X86";
23 let Namespace = "X86" in {
42 // variations by target as well. Currently the first entry is for X86-64,
43 // second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux
44 // and debug information on X86-32/Darwin)
60 // X86-64 only, requires REX.
91 // X86-64 only, requires REX.
115 // X86-64 only, requires REX
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/external/llvm/lib/Target/X86/MCTargetDesc/
DX86AsmBackend.cpp47 case X86::reloc_riprel_4byte: in getFixupKindLog2Size()
48 case X86::reloc_riprel_4byte_movq_load: in getFixupKindLog2Size()
49 case X86::reloc_signed_4byte: in getFixupKindLog2Size()
50 case X86::reloc_global_offset_table: in getFixupKindLog2Size()
75 return X86::NumTargetFixupKinds; in getNumFixupKinds()
79 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = { in getFixupKindInfo()
130 case X86::JAE_1: return X86::JAE_4; in getRelaxedOpcodeBranch()
131 case X86::JA_1: return X86::JA_4; in getRelaxedOpcodeBranch()
132 case X86::JBE_1: return X86::JBE_4; in getRelaxedOpcodeBranch()
133 case X86::JB_1: return X86::JB_4; in getRelaxedOpcodeBranch()
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DX86BaseInfo.h27 namespace X86 {
658 if ((RegNo > X86::XMM7 && RegNo <= X86::XMM15) || in isX86_64ExtendedReg()
659 (RegNo > X86::XMM23 && RegNo <= X86::XMM31) || in isX86_64ExtendedReg()
660 (RegNo > X86::YMM7 && RegNo <= X86::YMM15) || in isX86_64ExtendedReg()
661 (RegNo > X86::YMM23 && RegNo <= X86::YMM31) || in isX86_64ExtendedReg()
662 (RegNo > X86::ZMM7 && RegNo <= X86::ZMM15) || in isX86_64ExtendedReg()
663 (RegNo > X86::ZMM23 && RegNo <= X86::ZMM31)) in isX86_64ExtendedReg()
668 case X86::R8: case X86::R9: case X86::R10: case X86::R11: in isX86_64ExtendedReg()
669 case X86::R12: case X86::R13: case X86::R14: case X86::R15: in isX86_64ExtendedReg()
670 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D: in isX86_64ExtendedReg()
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/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp36 case X86::INSERTPSrr: in EmitAnyX86InstComments()
37 case X86::VINSERTPSrr: in EmitAnyX86InstComments()
44 case X86::MOVLHPSrr: in EmitAnyX86InstComments()
45 case X86::VMOVLHPSrr: in EmitAnyX86InstComments()
52 case X86::MOVHLPSrr: in EmitAnyX86InstComments()
53 case X86::VMOVHLPSrr: in EmitAnyX86InstComments()
60 case X86::PALIGNR128rr: in EmitAnyX86InstComments()
61 case X86::VPALIGNR128rr: in EmitAnyX86InstComments()
64 case X86::PALIGNR128rm: in EmitAnyX86InstComments()
65 case X86::VPALIGNR128rm: in EmitAnyX86InstComments()
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/external/llvm/test/Object/
Dobj2yaml.test2 RUN: obj2yaml %p/Inputs/trivial-object-test.coff-x86-64 | FileCheck %s --check-prefix COFF-X86-64
80 COFF-X86-64: header:
81 COFF-X86-64-NEXT: Machine: IMAGE_FILE_MACHINE_AMD64
83 COFF-X86-64: sections:
84 COFF-X86-64-NEXT: - Name: .text
85 COFF-X86-64-NEXT: Characteristics: [ IMAGE_SCN_CNT_CODE, IMAGE_SCN_MEM_EXECUTE, IMAGE_SCN_MEM_R…
86 COFF-X86-64-NEXT: Alignment: 16
87 COFF-X86-64-NEXT: SectionData: 4883EC28C744242400000000488D0D00000000E800000000E8000000008B4424…
89 COFF-X86-64: Relocations:
90 COFF-X86-64-NEXT: - VirtualAddress: 15
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/external/llvm/test/tools/llvm-readobj/
Dprogram-headers.test4 RUN: | FileCheck %s -check-prefix ELF-X86-64
35 ELF-X86-64: ProgramHeaders [
36 ELF-X86-64-NEXT: ProgramHeader {
37 ELF-X86-64-NEXT: Type: PT_LOAD (0x1)
38 ELF-X86-64-NEXT: Offset: 0x0
39 ELF-X86-64-NEXT: VirtualAddress: 0x400000
40 ELF-X86-64-NEXT: PhysicalAddress: 0x400000
41 ELF-X86-64-NEXT: FileSize: 312
42 ELF-X86-64-NEXT: MemSize: 312
43 ELF-X86-64-NEXT: Flags [ (0x5)
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/external/llvm/test/CodeGen/X86/
Dh-registers-0.ll1 ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=X86-64
3 ; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X86-32
9 ; X86-64-LABEL: bar64:
10 ; X86-64: shrq $8, %rdi
11 ; X86-64: incb %dil
19 ; X86-32-LABEL: bar64:
20 ; X86-32: incb %ah
29 ; X86-64-LABEL: bar32:
30 ; X86-64: shrl $8, %edi
31 ; X86-64: incb %dil
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Dvec_shuffle-14.ll1 ; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s -check-prefix=X86-32
2 ; RUN: llc < %s -march=x86-64 -mattr=+sse2 | FileCheck %s -check-prefix=X86-64
10 ; X86-32-LABEL: t1:
11 ; X86-32: movd 4(%esp), %xmm0
13 ; X86-64-LABEL: t1:
14 ; X86-64: movd %e{{..}}, %xmm0
23 ; X86-32-LABEL: t2:
24 ; X86-32: movq 4(%esp), %xmm0
26 ; X86-64-LABEL: t2:
27 ; X86-64: movd %r{{..}}, %xmm0
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Dmmx-arg-passing.ll1 ; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+mmx | FileCheck %s -check-prefix=X86-32
2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | FileCheck %s -check-prefix=X86-64
16 ; X86-32-LABEL: t1:
17 ; X86-32: movq %mm0
19 ; X86-64-LABEL: t1:
20 ; X86-64: movdq2q %xmm0
21 ; X86-64: movq %mm0
31 ; X86-32-LABEL: t2:
32 ; X86-32: movl 4(%esp)
33 ; X86-32: movl 8(%esp)
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Dmemset.ll1 …lc < %s -march=x86 -mcpu=pentium2 -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefix=X86
14 ; X86: movl $0,
15 ; X86: movl $0,
16 ; X86: movl $0,
17 ; X86: movl $0,
18 ; X86: movl $0,
19 ; X86: movl $0,
20 ; X86: movl $0,
21 ; X86: movl $0,
22 ; X86-NOT: movl $0,
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/external/llvm/lib/Target/X86/Disassembler/
DX86Disassembler.cpp56 namespace X86 { namespace
159 #define ENTRY(x) X86::x, in translateRegister()
257 if (Opcode != X86::BLENDPSrri && Opcode != X86::BLENDPDrri && in translateImmediate()
258 Opcode != X86::PBLENDWrri && Opcode != X86::MPSADBWrri && in translateImmediate()
259 Opcode != X86::DPPSrri && Opcode != X86::DPPDrri && in translateImmediate()
260 Opcode != X86::INSERTPSrr && Opcode != X86::VBLENDPSYrri && in translateImmediate()
261 Opcode != X86::VBLENDPSYrmi && Opcode != X86::VBLENDPDYrri && in translateImmediate()
262 Opcode != X86::VBLENDPDYrmi && Opcode != X86::VPBLENDWrri && in translateImmediate()
263 Opcode != X86::VMPSADBWrri && Opcode != X86::VDPPSYrri && in translateImmediate()
264 Opcode != X86::VDPPSYrmi && Opcode != X86::VDPPDrri && in translateImmediate()
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/external/llvm/test/MC/COFF/
Dweak-symbol.ll5 ; RUN: llc -mtriple=i686-pc-win32 %s -o - | FileCheck %s --check-prefix=X86
6 ; RUN: llc -mtriple=i686-pc-mingw32 %s -o - | FileCheck %s --check-prefix=X86
11 ; X86: .section .text$_Z3foo
12 ; X86: .linkonce discard
13 ; X86: .globl __Z3foo
23 ; X86: .section .sect$f
24 ; X86: .linkonce discard
25 ; X86: .globl _f
35 ; X86: .section .data$a
36 ; X86: .linkonce discard
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/external/clang/test/CodeGenObjC/
Dvariadic-sends.m1 …own -fobjc-runtime=macosx-fragile-10.5 -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-X86-32 %s
2 …own -fobjc-runtime=macosx-fragile-10.5 -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-X86-64 %s
11 // CHECK-X86-32: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*)*)
12 // CHECK-X86-64: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*)*)
17 // CHECK-X86-32: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i32)*)
18 // CHECK-X86-64: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i32)*)
23 …// CHECK-X86-32: call void (i8*, i8*, i32, ...)* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to vo…
24 …// CHECK-X86-64: call void (i8*, i8*, i32, ...)* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to vo…
31 …// CHECK-X86-32: call void bitcast (i8* (%struct._objc_super*, i8*, ...)* @objc_msgSendSuper to vo…
32 …// CHECK-X86-64: call void bitcast (i8* (%struct._objc_super*, i8*, ...)* @objc_msgSendSuper to vo…
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/external/valgrind/main/VEX/auxprogs/
Dgenoffsets.c83 GENOFFSET(X86,x86,EAX); in foo()
84 GENOFFSET(X86,x86,EBX); in foo()
85 GENOFFSET(X86,x86,ECX); in foo()
86 GENOFFSET(X86,x86,EDX); in foo()
87 GENOFFSET(X86,x86,ESI); in foo()
88 GENOFFSET(X86,x86,EDI); in foo()
89 GENOFFSET(X86,x86,EBP); in foo()
90 GENOFFSET(X86,x86,ESP); in foo()
91 GENOFFSET(X86,x86,EIP); in foo()
92 GENOFFSET(X86,x86,CS); in foo()
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/external/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp538 return (STI.getFeatureBits() & X86::Mode64Bit) != 0; in is64BitMode()
541 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(X86::Mode64Bit)); in SwitchMode()
820 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15; in isMemVX32()
824 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15; in isMemVY32()
828 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15; in isMemVX64()
832 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15; in isMemVY64()
836 getMemIndexReg() >= X86::ZMM0 && getMemIndexReg() <= X86::ZMM31; in isMemVZ32()
840 getMemIndexReg() >= X86::ZMM0 && getMemIndexReg() <= X86::ZMM31; in isMemVZ64()
1010 unsigned basereg = is64BitMode() ? X86::RSI : X86::ESI; in isSrcOp()
1013 (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::DS) && in isSrcOp()
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