Searched refs:XAssisted (Results 1 – 10 of 10) sorted by relevance
| /external/valgrind/main/VEX/priv/ |
| D | host_amd64_defs.c | 729 i->Ain.XAssisted.dstGA = dstGA; in AMD64Instr_XAssisted()
730 i->Ain.XAssisted.amRIP = amRIP; in AMD64Instr_XAssisted()
731 i->Ain.XAssisted.cond = cond; in AMD64Instr_XAssisted()
732 i->Ain.XAssisted.jk = jk; in AMD64Instr_XAssisted()
1104 showAMD64CondCode(i->Ain.XAssisted.cond)); in ppAMD64Instr()
1106 ppHRegAMD64(i->Ain.XAssisted.dstGA); in ppAMD64Instr()
1108 ppAMD64AMode(i->Ain.XAssisted.amRIP); in ppAMD64Instr()
1110 (Int)i->Ain.XAssisted.jk); in ppAMD64Instr()
1455 addHRegUse(u, HRmRead, i->Ain.XAssisted.dstGA); in getRegUsage_AMD64Instr()
1456 addRegUsage_AMD64AMode(u, i->Ain.XAssisted.amRIP); in getRegUsage_AMD64Instr()
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| D | host_mips_defs.c | 1274 i->Min.XAssisted.dstGA = dstGA; in MIPSInstr_XAssisted()
1275 i->Min.XAssisted.amPC = amPC; in MIPSInstr_XAssisted()
1276 i->Min.XAssisted.cond = cond; in MIPSInstr_XAssisted()
1277 i->Min.XAssisted.jk = jk; in MIPSInstr_XAssisted()
1639 showMIPSCondCode(i->Min.XAssisted.cond)); in ppMIPSInstr()
1641 ppHRegMIPS(i->Min.XAssisted.dstGA, mode64); in ppMIPSInstr()
1643 ppMIPSAMode(i->Min.XAssisted.amPC, mode64); in ppMIPSInstr()
1645 (Int)i->Min.XAssisted.jk); in ppMIPSInstr()
1924 addHRegUse(u, HRmRead, i->Min.XAssisted.dstGA); in getRegUsage_MIPSInstr()
1925 addRegUsage_MIPSAMode(u, i->Min.XAssisted.amPC); in getRegUsage_MIPSInstr()
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| D | host_x86_defs.c | 673 i->Xin.XAssisted.dstGA = dstGA; in X86Instr_XAssisted()
674 i->Xin.XAssisted.amEIP = amEIP; in X86Instr_XAssisted()
675 i->Xin.XAssisted.cond = cond; in X86Instr_XAssisted()
676 i->Xin.XAssisted.jk = jk; in X86Instr_XAssisted()
1011 showX86CondCode(i->Xin.XAssisted.cond)); in ppX86Instr()
1013 ppHRegX86(i->Xin.XAssisted.dstGA); in ppX86Instr()
1015 ppX86AMode(i->Xin.XAssisted.amEIP); in ppX86Instr()
1017 (Int)i->Xin.XAssisted.jk); in ppX86Instr()
1329 addHRegUse(u, HRmRead, i->Xin.XAssisted.dstGA); in getRegUsage_X86Instr()
1330 addRegUsage_X86AMode(u, i->Xin.XAssisted.amEIP); in getRegUsage_X86Instr()
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| D | host_arm_defs.c | 1204 i->ARMin.XAssisted.dstGA = dstGA; in ARMInstr_XAssisted()
1205 i->ARMin.XAssisted.amR15T = amR15T; in ARMInstr_XAssisted()
1206 i->ARMin.XAssisted.cond = cond; in ARMInstr_XAssisted()
1207 i->ARMin.XAssisted.jk = jk; in ARMInstr_XAssisted()
1650 showARMCondCode(i->ARMin.XAssisted.cond)); in ppARMInstr()
1652 ppHRegARM(i->ARMin.XAssisted.dstGA); in ppARMInstr()
1654 ppARMAMode1(i->ARMin.XAssisted.amR15T); in ppARMInstr()
1656 (Int)i->ARMin.XAssisted.jk); in ppARMInstr()
2058 addHRegUse(u, HRmRead, i->ARMin.XAssisted.dstGA); in getRegUsage_ARMInstr()
2059 addRegUsage_ARMAMode1(u, i->ARMin.XAssisted.amR15T); in getRegUsage_ARMInstr()
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| D | host_ppc_defs.c | 877 i->Pin.XAssisted.dstGA = dstGA; in PPCInstr_XAssisted()
878 i->Pin.XAssisted.amCIA = amCIA; in PPCInstr_XAssisted()
879 i->Pin.XAssisted.cond = cond; in PPCInstr_XAssisted()
880 i->Pin.XAssisted.jk = jk; in PPCInstr_XAssisted()
1596 showPPCCondCode(i->Pin.XAssisted.cond)); in ppPPCInstr()
1598 ppHRegPPC(i->Pin.XAssisted.dstGA); in ppPPCInstr()
1600 ppPPCAMode(i->Pin.XAssisted.amCIA); in ppPPCInstr()
1603 (Int)i->Pin.XAssisted.jk); in ppPPCInstr()
2242 addHRegUse(u, HRmRead, i->Pin.XAssisted.dstGA); in getRegUsage_PPCInstr()
2243 addRegUsage_PPCAMode(u, i->Pin.XAssisted.amCIA); in getRegUsage_PPCInstr()
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| D | host_x86_defs.h | 474 } XAssisted; member
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| D | host_amd64_defs.h | 496 } XAssisted; member
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| D | host_mips_defs.h | 516 } XAssisted; member
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| D | host_arm_defs.h | 709 } XAssisted; member
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| D | host_ppc_defs.h | 639 } XAssisted; member
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