| /external/llvm/lib/CodeGen/ |
| D | ProcessImplicitDefs.cpp | 71 if (MO->isReg() && MO->isUse() && MO->readsReg()) in canTurnIntoImplicitDef()
114 if (MO->isUse()) in processImplicitDef()
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| D | MachineInstr.cpp | 300 if (isUndef() && isUse()) { in print()
699 if (NewMO->isUse()) { in addOperand()
964 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
1001 if (!MO.isReg() || !MO.isUse()) in findRegisterUseOperandIdx()
1033 if (MO.isUse()) in readsWritesVirtualRegister()
1113 assert(UseMO.isUse() && "UseIdx must be a use operand"); in tieOperands()
1145 if (MO.isUse()) in findTiedOperandIdx()
1150 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1) in findTiedOperandIdx()
1194 if (MO.isReg() && MO.isUse()) in clearKillInfo()
1357 if (!MO.isReg() || MO.isUse()) in allDefsAreDead()
[all …]
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| D | ExpandPostRAPseudos.cpp | 72 if (!MO.isReg() || !MO.isImplicit() || MO.isUse()) in TransferImplicitDefs()
82 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && in LowerSubregToReg()
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| D | Spiller.cpp | 113 hasUse |= mi->getOperand(i).isUse(); in trivialSpillEverywhere()
127 if (mop.isUse() && !mi->isRegTiedToDefOperand(mopIdx)) { in trivialSpillEverywhere()
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| D | TwoAddressInstructionPass.cpp | 200 if (MO.isUse() && MOReg != SavedReg) in sink3AddrInstruction()
327 if (MO.isUse() && DI->second < LastUse) in noUseAfterLastDef()
438 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) in isTwoAddrUse()
991 if (MO.isUse()) { in rescheduleKillAboveMI()
1032 if (MO.isUse()) { in rescheduleKillAboveMI()
1237 if (MO.isUse()) { in tryInstructionTransform()
1317 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid"); in collectTiedOperands()
1410 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() && in processTiedPairs()
1434 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) { in processTiedPairs()
1470 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) { in processTiedPairs()
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| D | RegisterScavenging.cpp | 136 if (MO.isUse()) { in determineKillsAndDefs()
207 if (MO.isUse()) { in forward()
371 if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) && in scavengeRegister()
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| D | RegAllocFast.cpp | 236 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) { in addKillFlag()
599 if (LRI->LastUse != MI || LRI->LastUse->getOperand(LRI->LastOpNum).isUse()) in defineVirtReg()
631 if (MO.isUse()) in reloadVirtReg()
731 if (MO.isUse()) { in handleThroughOperands()
915 if (MO.isUse()) { in AllocateBasicBlock()
927 if (MO.isUse()) { in AllocateBasicBlock()
963 if (MO.isUse()) { in AllocateBasicBlock()
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| D | CriticalAntiDepBreaker.cpp | 202 if (MO.isUse() && Special) { in PrescanInstruction()
268 if (!MO.isUse()) continue; in ScanInstruction()
581 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) { in BreakAntiDependencies()
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| D | MachineCSE.cpp | 119 if (!MO.isReg() || !MO.isUse()) in INITIALIZE_PASS_DEPENDENCY()
173 if (MO.isUse()) in isPhysDefTriviallyDead()
383 if (MO.isReg() && MO.isUse() && in isProfitableToCSE()
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| D | TargetInstrInfo.cpp | 415 assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!"); in foldMemoryOperand()
487 if (MO.isUse()) { in isReallyTriviallyReMaterializableGeneric()
508 if (MO.isUse()) in isReallyTriviallyReMaterializableGeneric()
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| D | LiveIntervalAnalysis.cpp | 623 LiveIntervals::getSpillWeight(bool isDef, bool isUse, BlockFrequency freq) { in getSpillWeight() argument
625 return (isDef + isUse) * (freq.getFrequency() * Scale); in getSpillWeight()
746 if (MO->isUse()) in updateAllRanges()
828 if (MO->isReg() && MO->isUse()) in handleMoveDown()
1159 } else if (MO.isUse()) { in repairIntervalsInRange()
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| D | DeadMachineInstructionElim.cpp | 173 if (MO.isReg() && MO.isUse()) { in runOnMachineFunction()
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| D | MachineSink.cpp | 491 if (MO.isUse()) { in FindSuccToSinkTo()
503 if (MO.isUse()) continue; in FindSuccToSinkTo()
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| D | BranchFolding.cpp | 153 if (!MO.isReg() || !MO.isUse()) in OptimizeImpDefsBlock()
1496 if (MO.isUse()) { in findHoistingInsertPosAndDeps()
1523 if (!MO.isReg() || MO.isUse()) in findHoistingInsertPosAndDeps()
1557 if (MO.isUse()) { in findHoistingInsertPosAndDeps()
1688 if (!MO.isReg() || !MO.isUse() || !MO.isKill()) in HoistCommonCodeInSuccs()
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| D | PostRASchedulerList.cpp | 511 if (!MO.isReg() || !MO.isUse()) continue; in FixupKills()
546 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue; in FixupKills()
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| D | MachineLICM.cpp | 934 if (MO.isUse()) { in IsLoopInvariantInst()
952 if (!MO.isUse()) in IsLoopInvariantInst()
1023 if (!MO.isReg() || !MO.isUse()) in HasHighOperandLatency()
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| /external/llvm/lib/Target/Sparc/ |
| D | DelaySlotFiller.cpp | 248 if (MO.isUse()) { in delayHasHazard()
273 assert(Reg.isUse() && "JMPL first operand is not a use."); in insertCallDefsUses()
280 assert(RegOrImm.isUse() && "JMPLrr second operand is not a use."); in insertCallDefsUses()
301 if (MO.isUse()) { in insertDefsUses()
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| /external/llvm/lib/Target/R600/ |
| D | SIInsertWaits.cpp | 175 if (I->isReg() && I->isUse()) in isOpRelevant()
233 if (Op.isUse()) in pushInstruction()
325 if (Op.isUse()) in handleOperands()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonNewValueJump.cpp | 151 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) { in INITIALIZE_PASS_DEPENDENCY()
573 if (MO.isReg() && MO.isUse()) { in runOnMachineFunction()
580 if (localMO.isReg() && localMO.isUse() && in runOnMachineFunction()
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| D | HexagonVLIWPacketizer.cpp | 356 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) { in IsCallDependent()
490 MI->getOperand(opNum).isUse()) { in GetPostIncrementOperand()
851 if (Op.isReg() && Op.getReg() && Op.isUse() && in getPredicatedRegister()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineRegisterInfo.h | 529 if ((!ReturnUses && op->isUse()) || in defusechain_iterator()
563 if (Op->isUse())
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| D | MachineOperand.h | 269 bool isUse() const { in isUse() function
328 return !isUndef() && !isInternalRead() && (isUse() || getSubReg()); in readsReg()
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| D | LiveIntervalAnalysis.h | 103 static float getSpillWeight(bool isDef, bool isUse, BlockFrequency freq);
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2ITBlockPass.cpp | 68 if (MO.isUse()) in TrackDefUses()
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| D | A15SDOptimizer.cpp | 200 if ((!MO.isReg()) || (!MO.isUse())) in eraseInstrWithNoUses()
418 if (!MO.isReg() || !MO.isUse()) in getReadDPRs()
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