| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 216 // Register list of one D register, with byte lane subscripting.
226 // ...with half-word lane subscripting.
236 // ...with word lane subscripting.
247 // Register list of two D registers with byte lane subscripting.
257 // ...with half-word lane subscripting.
267 // ...with word lane subscripting.
277 // Register list of two Q registers with half-word lane subscripting.
287 // ...with word lane subscripting.
299 // Register list of three D registers with byte lane subscripting.
309 // ...with half-word lane subscripting.
[all …]
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| D | ARMInstrFormats.td | 1877 bits<3> lane;
2114 bit lane;
2121 let Inst{5} = lane;
2135 bits<2> lane;
2142 let Inst{5} = lane{1};
2143 let Inst{3} = lane{0};
2197 bits<4> lane;
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| D | ARMScheduleSwift.td | 1939 // Single all/lane loads.
2021 // Single/all lane store.
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| D | ARMInstrInfo.td | 963 // (single element from one lane) for size 32.
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| /external/llvm/test/CodeGen/ARM/ |
| D | 2012-05-04-vmov.ll | 10 ; vmov.32 should not be used to get a lane:
11 ; vmov.32 <dst>, <src>[<lane>].
12 ; but vmov.32 <dst>[<lane>], <src> is fine.
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| D | a15-partial-update.ll | 6 ; to write the lane 1 of a D register containing the value of
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| D | coalesce-subregs.ll | 71 ; This function has lane insertions that span basic blocks.
120 ; This function inserts a lane into a fully defined vector.
121 ; The destination lane isn't read, so the subregs can coalesce.
152 ; It is inserting the %add value into a dead lane, but %add causes interference
153 ; in the entry block, and we don't do dead lane checks across basic blocks.
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| D | vget_lane.ll | 218 ; The llvm extractelement instruction does not require that the lane number
219 ; be an immediate constant. Make sure a variable lane number is handled.
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| /external/llvm/test/CodeGen/Thumb2/ |
| D | 2013-03-02-vduplane-nonconstant-source-index.ll | 3 define void @bar(<4 x i32>* %p, i32 %lane, <4 x i32> %phitmp) nounwind {
8 %val = extractelement <4 x i32> %phitmp, i32 %lane
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| /external/llvm/include/llvm/IR/ |
| D | IntrinsicsARM.td | 392 // Vector load N-element structure to one lane.
394 // lane is assigned), the lane number, and the alignment.
431 // Vector store N-element structure from one lane.
432 // Source operands are: the address, the N vectors, the lane number, and
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| /external/tcpdump/ |
| D | FILES | 64 lane.h
161 print-lane.c
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| D | Android.mk | 64 print-lane.c\
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| D | Makefile.in | 80 print-l2tp.c print-lane.c print-ldp.c print-llc.c \
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| D | INSTALL | 105 lane.h - ATM LANE definitions
178 print-lane.c - ATM LANE printer routines
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| D | nv50_ir_emit_nv50.cpp | 120 void emitQUADOP(const Instruction *, uint8_t lane, uint8_t quOp);
779 CodeEmitterNV50::emitQUADOP(const Instruction *i, uint8_t lane, uint8_t quOp) in emitQUADOP() argument
781 code[0] = 0xc0000000 | (lane << 16); in emitQUADOP()
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| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| D | nv50_ir_emit_nv50.cpp | 120 void emitQUADOP(const Instruction *, uint8_t lane, uint8_t quOp);
779 CodeEmitterNV50::emitQUADOP(const Instruction *i, uint8_t lane, uint8_t quOp) in emitQUADOP() argument
781 code[0] = 0xc0000000 | (lane << 16); in emitQUADOP()
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| /external/libpcap/ |
| D | scanner.l | 269 lane return LANE;
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| /external/clang/utils/TableGen/ |
| D | NeonEmitter.cpp | 1271 const std::string &lane) { in SplatLane() argument
1274 s += ", " + lane; in SplatLane()
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| /external/valgrind/main/VEX/priv/ |
| D | guest_x86_toIR.c | 8957 Int lane; in disInstr_X86_WRK() local
8970 lane = insn[3+1-1]; in disInstr_X86_WRK()
8971 DIP("pinsrw $%d,%s,%s\n", (Int)lane, in disInstr_X86_WRK()
8977 lane = insn[3+alen-1]; in disInstr_X86_WRK()
8979 DIP("pinsrw $%d,%s,%s\n", (Int)lane, in disInstr_X86_WRK()
8984 switch (lane & 3) { in disInstr_X86_WRK()
10785 Int lane; in disInstr_X86_WRK() local
10792 lane = insn[3+1-1]; in disInstr_X86_WRK()
10793 DIP("pinsrw $%d,%s,%s\n", (Int)lane, in disInstr_X86_WRK()
10799 lane = insn[3+alen-1]; in disInstr_X86_WRK()
[all …]
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| D | guest_amd64_toIR.c | 13158 Int lane; in dis_ESC_0F__SSE2() local
13171 lane = getUChar(delta-1); in dis_ESC_0F__SSE2()
13172 DIP("pinsrw $%d,%s,%s\n", (Int)lane, in dis_ESC_0F__SSE2()
13178 lane = getUChar(delta-1); in dis_ESC_0F__SSE2()
13180 DIP("pinsrw $%d,%s,%s\n", (Int)lane, in dis_ESC_0F__SSE2()
13185 switch (lane & 3) { in dis_ESC_0F__SSE2()
13199 Int lane; in dis_ESC_0F__SSE2() local
13207 lane = getUChar(delta-1); in dis_ESC_0F__SSE2()
13209 (Int)lane, nameIReg16(rE), nameXMMReg(rG)); in dis_ESC_0F__SSE2()
13214 lane = getUChar(delta-1); in dis_ESC_0F__SSE2()
[all …]
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| /external/valgrind/main/none/tests/arm/ |
| D | neon64.stdout.exp | 1992 ---- VLD1 (single element to one lane) ----
2027 ---- VLD2 (single 2-element structure to one lane) ----
2065 ---- VLD3 (single 3-element structure to one lane) ----
2103 ---- VLD4 (single 4-element structure to one lane) ----
2155 ---- VST1 (single element from one lane) ----
2180 ---- VST2 (single 2-element structure from one lane) ----
2208 ---- VST3 (single 3-element structure from one lane) ----
2236 ---- VST4 (single 4-element structure from one lane) ----
2278 ---- VLD1 (single element to one lane) ----
2313 ---- VLD2 (single 2-element structure to one lane) ----
[all …]
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| /external/chromium/net/base/ |
| D | ssl_false_start_blacklist.txt | 3923 vpn.4j.lane.edu
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| /external/chromium_org/third_party/sqlite/src/test/ |
| D | fts1porter.test | 11615 lane lane
11616 lanes lane
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| /external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/textana/en-US/ |
| D | en-US_tpp_net.utf | 400 1559 "lane"
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| /external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/textana/en-GB/ |
| D | en-GB_tpp_net.utf | 400 1563 "lane"
|