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Searched refs:reg3 (Results 1 – 19 of 19) sorted by relevance

/external/llvm/test/CodeGen/ARM/
Dfast-isel-pic.ll28 ; ARMv7-ELF: ldr r[[reg3:[0-9]+]],
29 ; ARMv7-ELF: ldr r[[reg2]], [r[[reg3]], r[[reg2]]]
39 ; THUMB: movw r[[reg3:[0-9]+]],
40 ; THUMB: movt r[[reg3]],
41 ; THUMB: add r[[reg3]], pc
42 ; THUMB: ldr r[[reg3]], [r[[reg3]]]
44 ; THUMB-ELF: ldr r[[reg3:[0-9]+]],
46 ; THUMB-ELF: ldr r[[reg3]], [r[[reg3]], r[[reg4]]]
/external/valgrind/main/none/tests/s390x/
Dcksm.c27 register uint64_t reg3 asm("3") = len; in cksm_by_insn()
33 : "+d" (sum), "+d" (reg2), "+d" (reg3) : : "cc", "memory"); in cksm_by_insn()
36 len = reg3; in cksm_by_insn()
/external/pixman/pixman/
Dpixman-arm-neon-asm.h92 .macro pixldst4 op, elem_size, reg1, reg2, reg3, reg4, mem_operand, abits
94 op&.&elem_size {d&reg1, d&reg2, d&reg3, d&reg4}, [&mem_operand&, :&abits&]!
96 op&.&elem_size {d&reg1, d&reg2, d&reg3, d&reg4}, [&mem_operand&]!
104 .macro pixldst3 op, elem_size, reg1, reg2, reg3, mem_operand
105 op&.&elem_size {d&reg1, d&reg2, d&reg3}, [&mem_operand&]!
108 .macro pixldst30 op, elem_size, reg1, reg2, reg3, idx, mem_operand
109 op&.&elem_size {d&reg1[idx], d&reg2[idx], d&reg3[idx]}, [&mem_operand&]!
Dpixman-arm-simd-asm.h99 .macro pixldst op, cond=al, numbytes, reg0, reg1, reg2, reg3, base, unaligned=0
105 op&r&cond WK&reg3, [base], #4
107 op&m&cond&ia base!, {WK&reg0,WK&reg1,WK&reg2,WK&reg3}
127 .macro pixst_baseupdated cond, numbytes, reg0, reg1, reg2, reg3, base
129 stm&cond&db base, {WK&reg0,WK&reg1,WK&reg2,WK&reg3}
Dpixman-arm-neon-asm-bilinear.S109 acc1, acc2, reg1, reg2, reg3, reg4, tmp1, tmp2
114 bilinear_load_8888 reg3, reg4, tmp2
115 vmull.u8 acc2, reg3, d28
130 acc1, acc2, reg1, reg2, reg3, reg4, acc2lo, acc2hi
142 convert_0565_to_x888 acc2, reg3, reg2, reg1
143 vzip.u8 reg1, reg3
145 vzip.u8 reg3, reg4
149 vmull.u8 acc2, reg3, d28
Dpixman-arm-simd-asm.S374 .macro over_8888_8888_check_transparent numbytes, reg0, reg1, reg2, reg3 argument
381 teqeq WK&reg3, #0
Dpixman-arm-neon-asm.S2868 acc1, acc2, reg1, reg2, reg3, reg4, tmp1, tmp2
2873 bilinear_load_8888 reg3, reg4, tmp2
2874 vmull.u8 acc2, reg3, d28
2889 acc1, acc2, reg1, reg2, reg3, reg4, acc2lo, acc2hi
2901 convert_0565_to_x888 acc2, reg3, reg2, reg1
2902 vzip.u8 reg1, reg3
2904 vzip.u8 reg3, reg4
2908 vmull.u8 acc2, reg3, d28
/external/skia/gm/
Dcomplexclip2.cpp176 static GMRegistry reg3(MyFactory3);
Dbitmaprect.cpp251 static skiagm::GMRegistry reg3(MyFactory3);
Dgradients.cpp435 static GMRegistry reg3(MyFactory3);
/external/chromium_org/third_party/sqlite/src/src/
Dbuild.c868 int reg1, reg2, reg3; in sqlite3StartTable() local
882 reg3 = ++pParse->nMem; in sqlite3StartTable()
883 sqlite3VdbeAddOp3(v, OP_ReadCookie, iDb, reg3, BTREE_FILE_FORMAT); in sqlite3StartTable()
885 j1 = sqlite3VdbeAddOp1(v, OP_If, reg3); in sqlite3StartTable()
888 sqlite3VdbeAddOp2(v, OP_Integer, fileFormat, reg3); in sqlite3StartTable()
889 sqlite3VdbeAddOp3(v, OP_SetCookie, iDb, BTREE_FILE_FORMAT, reg3); in sqlite3StartTable()
890 sqlite3VdbeAddOp2(v, OP_Integer, ENC(db), reg3); in sqlite3StartTable()
891 sqlite3VdbeAddOp3(v, OP_SetCookie, iDb, BTREE_TEXT_ENCODING, reg3); in sqlite3StartTable()
913 sqlite3VdbeAddOp2(v, OP_Null, 0, reg3); in sqlite3StartTable()
914 sqlite3VdbeAddOp3(v, OP_Insert, 0, reg3, reg1); in sqlite3StartTable()
/external/chromium_org/v8/src/arm/
Dmacro-assembler-arm.cc3971 Register reg3, in GetRegisterThatIsNotOneOf() argument
3978 if (reg3.is_valid()) regs |= reg3.bit(); in GetRegisterThatIsNotOneOf()
4022 Register reg3, in AreAliased() argument
4027 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid(); in AreAliased()
4032 if (reg3.is_valid()) regs |= reg3.bit(); in AreAliased()
Dmacro-assembler-arm.h68 Register reg3 = no_reg,
77 Register reg3 = no_reg,
/external/libvpx/libvpx/vp9/common/arm/neon/
Dvp9_short_idct32x32_add_neon.asm241 …DO_BUTTERFLY $regC, $regD, $regA, $regB, $first_constant, $second_constant, $reg1, $reg2, $reg3, $…
278 vqrshrn.s32 $reg3, q11, #14
286 DO_BUTTERFLY_STD $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg4
287 DO_BUTTERFLY d28, d29, d26, d27, $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg4
/external/chromium_org/v8/src/mips/
Dmacro-assembler-mips.h101 Register reg3 = no_reg,
Dmacro-assembler-mips.cc5661 Register reg3, in GetRegisterThatIsNotOneOf() argument
5668 if (reg3.is_valid()) regs |= reg3.bit(); in GetRegisterThatIsNotOneOf()
/external/chromium_org/third_party/sqlite/amalgamation/
Dsqlite3.c77884 int reg1, reg2, reg3;
77898 reg3 = ++pParse->nMem;
77899 sqlite3VdbeAddOp3(v, OP_ReadCookie, iDb, reg3, BTREE_FILE_FORMAT);
77901 j1 = sqlite3VdbeAddOp1(v, OP_If, reg3);
77904 sqlite3VdbeAddOp2(v, OP_Integer, fileFormat, reg3);
77905 sqlite3VdbeAddOp3(v, OP_SetCookie, iDb, BTREE_FILE_FORMAT, reg3);
77906 sqlite3VdbeAddOp2(v, OP_Integer, ENC(db), reg3);
77907 sqlite3VdbeAddOp3(v, OP_SetCookie, iDb, BTREE_TEXT_ENCODING, reg3);
77929 sqlite3VdbeAddOp2(v, OP_Null, 0, reg3);
77930 sqlite3VdbeAddOp3(v, OP_Insert, 0, reg3, reg1);
/external/sqlite/dist/orig/
Dsqlite3.c82059 int reg1, reg2, reg3;
82073 reg3 = ++pParse->nMem;
82074 sqlite3VdbeAddOp3(v, OP_ReadCookie, iDb, reg3, BTREE_FILE_FORMAT);
82076 j1 = sqlite3VdbeAddOp1(v, OP_If, reg3);
82079 sqlite3VdbeAddOp2(v, OP_Integer, fileFormat, reg3);
82080 sqlite3VdbeAddOp3(v, OP_SetCookie, iDb, BTREE_FILE_FORMAT, reg3);
82081 sqlite3VdbeAddOp2(v, OP_Integer, ENC(db), reg3);
82082 sqlite3VdbeAddOp3(v, OP_SetCookie, iDb, BTREE_TEXT_ENCODING, reg3);
82104 sqlite3VdbeAddOp2(v, OP_Null, 0, reg3);
82105 sqlite3VdbeAddOp3(v, OP_Insert, 0, reg3, reg1);
/external/sqlite/dist/
Dsqlite3.c82095 int reg1, reg2, reg3;
82109 reg3 = ++pParse->nMem;
82110 sqlite3VdbeAddOp3(v, OP_ReadCookie, iDb, reg3, BTREE_FILE_FORMAT);
82112 j1 = sqlite3VdbeAddOp1(v, OP_If, reg3);
82115 sqlite3VdbeAddOp2(v, OP_Integer, fileFormat, reg3);
82116 sqlite3VdbeAddOp3(v, OP_SetCookie, iDb, BTREE_FILE_FORMAT, reg3);
82117 sqlite3VdbeAddOp2(v, OP_Integer, ENC(db), reg3);
82118 sqlite3VdbeAddOp3(v, OP_SetCookie, iDb, BTREE_TEXT_ENCODING, reg3);
82140 sqlite3VdbeAddOp2(v, OP_Null, 0, reg3);
82141 sqlite3VdbeAddOp3(v, OP_Insert, 0, reg3, reg1);