| /external/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 230 OutMI.setOpcode(NewOpc); in LowerUnaryToTwoAddr()
253 Inst.setOpcode(Opcode); in SimplifyShortImmForm()
281 Inst.setOpcode(NewOpcode); in SimplifyMOVSX()
332 Inst.setOpcode(Opcode); in SimplifyShortMoveForm()
337 OutMI.setOpcode(MI->getOpcode()); in Lower()
394 OutMI.setOpcode(X86::MOV32ri); in Lower()
429 OutMI.setOpcode(NewOpc); in Lower()
443 OutMI.setOpcode(NewOpc); in Lower()
457 OutMI.setOpcode(Opcode); in Lower()
465 OutMI.setOpcode(X86::RET); in Lower()
[all …]
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| /external/llvm/lib/Target/XCore/Disassembler/ |
| D | XCoreDisassembler.cpp | 292 Inst.setOpcode(XCore::STW_2rus); in Decode2OpInstructionFail()
295 Inst.setOpcode(XCore::LDW_2rus); in Decode2OpInstructionFail()
298 Inst.setOpcode(XCore::ADD_3r); in Decode2OpInstructionFail()
301 Inst.setOpcode(XCore::SUB_3r); in Decode2OpInstructionFail()
304 Inst.setOpcode(XCore::SHL_3r); in Decode2OpInstructionFail()
307 Inst.setOpcode(XCore::SHR_3r); in Decode2OpInstructionFail()
310 Inst.setOpcode(XCore::EQ_3r); in Decode2OpInstructionFail()
313 Inst.setOpcode(XCore::AND_3r); in Decode2OpInstructionFail()
316 Inst.setOpcode(XCore::OR_3r); in Decode2OpInstructionFail()
319 Inst.setOpcode(XCore::LDW_3r); in Decode2OpInstructionFail()
[all …]
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 137 Inst.setOpcode(Mips::DSLL32); in LowerLargeShift()
140 Inst.setOpcode(Mips::DSRL32); in LowerLargeShift()
143 Inst.setOpcode(Mips::DSRA32); in LowerLargeShift()
169 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU); in LowerDextDins()
175 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM); in LowerDextDins()
217 TmpInst.setOpcode (NewOpcode); in EncodeInstruction()
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| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 575 TmpInst.setOpcode(PPC::LA); in ProcessInstruction()
585 TmpInst.setOpcode(PPC::ADDI); in ProcessInstruction()
595 TmpInst.setOpcode(PPC::ADDIS); in ProcessInstruction()
605 TmpInst.setOpcode(PPC::ADDIC); in ProcessInstruction()
615 TmpInst.setOpcode(PPC::ADDICo); in ProcessInstruction()
627 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo); in ProcessInstruction()
641 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo); in ProcessInstruction()
655 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo); in ProcessInstruction()
670 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo); in ProcessInstruction()
684 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo); in ProcessInstruction()
[all …]
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1845 Inst.setOpcode(ARM::RFEDA); in DecodeMemMultipleWritebackInstruction()
1848 Inst.setOpcode(ARM::RFEDA_UPD); in DecodeMemMultipleWritebackInstruction()
1851 Inst.setOpcode(ARM::RFEDB); in DecodeMemMultipleWritebackInstruction()
1854 Inst.setOpcode(ARM::RFEDB_UPD); in DecodeMemMultipleWritebackInstruction()
1857 Inst.setOpcode(ARM::RFEIA); in DecodeMemMultipleWritebackInstruction()
1860 Inst.setOpcode(ARM::RFEIA_UPD); in DecodeMemMultipleWritebackInstruction()
1863 Inst.setOpcode(ARM::RFEIB); in DecodeMemMultipleWritebackInstruction()
1866 Inst.setOpcode(ARM::RFEIB_UPD); in DecodeMemMultipleWritebackInstruction()
1869 Inst.setOpcode(ARM::SRSDA); in DecodeMemMultipleWritebackInstruction()
1872 Inst.setOpcode(ARM::SRSDA_UPD); in DecodeMemMultipleWritebackInstruction()
[all …]
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 5661 TmpInst.setOpcode(ARM::ADR); in processInstruction()
5676 Inst.setOpcode(ARM::tLDRpci); in processInstruction()
5678 Inst.setOpcode(ARM::t2LDRpci); in processInstruction()
5681 Inst.setOpcode(ARM::t2LDRBpci); in processInstruction()
5684 Inst.setOpcode(ARM::t2LDRHpci); in processInstruction()
5687 Inst.setOpcode(ARM::t2LDRSBpci); in processInstruction()
5690 Inst.setOpcode(ARM::t2LDRSHpci); in processInstruction()
5700 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
5722 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
5746 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); in processInstruction()
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.cpp | 38 NopInst.setOpcode(ARM::HINT); in getNoopForMachoTarget()
43 NopInst.setOpcode(ARM::MOVr); in getNoopForMachoTarget()
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| D | ARMMCInstLower.cpp | 116 OutMI.setOpcode(MI->getOpcode()); in LowerARMMachineInstrToMCInst()
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| D | Thumb1InstrInfo.cpp | 30 NopInst.setOpcode(ARM::tMOVr); in getNoopForMachoTarget()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 452 NopInst.setOpcode(Mips::SLL); in processInstruction()
539 tmpInst.setOpcode(Mips::ORi); in expandLoadImm()
547 tmpInst.setOpcode(Mips::ADDiu); in expandLoadImm()
556 tmpInst.setOpcode(Mips::LUi); in expandLoadImm()
561 tmpInst.setOpcode(Mips::ORi); in expandLoadImm()
583 tmpInst.setOpcode(Mips::ADDiu); in expandLoadAddressReg()
593 tmpInst.setOpcode(Mips::LUi); in expandLoadAddressReg()
598 tmpInst.setOpcode(Mips::ORi); in expandLoadAddressReg()
604 tmpInst.setOpcode(Mips::ADDu); in expandLoadAddressReg()
623 tmpInst.setOpcode(Mips::ADDiu); in expandLoadAddressImm()
[all …]
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| /external/llvm/include/llvm/MC/ |
| D | MCInstBuilder.h | 28 Inst.setOpcode(Opcode); in MCInstBuilder()
|
| D | MCInst.h | 157 void setOpcode(unsigned Op) { Opcode = Op; }
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUMCInstLower.cpp | 31 OutMI.setOpcode(MI->getOpcode()); in lower()
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | AMDGPUMCInstLower.cpp | 31 OutMI.setOpcode(MI->getOpcode()); in lower()
|
| /external/llvm/lib/Target/R600/ |
| D | AMDGPUMCInstLower.cpp | 34 OutMI.setOpcode(MI->getOpcode()); in lower()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonMCInstLower.cpp | 44 MCI.setOpcode(MI->getOpcode()); in HexagonLowerToMC()
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| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86Disassembler.cpp | 690 mcInst.setOpcode(insn.instructionID); in translateInstruction()
696 mcInst.setOpcode(X86::XRELEASE_PREFIX); in translateInstruction()
698 mcInst.setOpcode(X86::XACQUIRE_PREFIX); in translateInstruction()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZMCInstLower.cpp | 101 OutMI.setOpcode(Opcode); in lower()
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreMCInstLower.cpp | 108 OutMI.setOpcode(MI->getOpcode()); in Lower()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430MCInstLower.cpp | 110 OutMI.setOpcode(MI->getOpcode()); in Lower()
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| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 521 Inst.setOpcode(AArch64::LSLxxi); in DecodeBitfieldInstruction()
525 Inst.setOpcode(AArch64::LSLwwi); in DecodeBitfieldInstruction()
556 Inst.setOpcode(InsertOp); in DecodeBitfieldInstruction()
558 Inst.setOpcode(ExtractOp); in DecodeBitfieldInstruction()
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| /external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| D | SystemZMCAsmBackend.cpp | 136 Res.setOpcode(Opcode); in relaxInstruction()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCAsmPrinter.cpp | 359 TmpInst.setOpcode(PPC::LD); in EmitInstruction()
390 TmpInst.setOpcode(PPC::ADDIS8); in EmitInstruction()
433 TmpInst.setOpcode(PPC::LD); in EmitInstruction()
470 TmpInst.setOpcode(PPC::ADDI8); in EmitInstruction()
520 TmpInst.setOpcode(PPC::LD); in EmitInstruction()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64MCInstLower.cpp | 148 OutMI.setOpcode(MI->getOpcode()); in LowerAArch64MachineInstrToMCInst()
|
| /external/smack/src/org/xbill/DNS/ |
| D | Header.java | 190 setOpcode(int value) { in setOpcode() method in Header
|