| /external/oprofile/module/ia64/ |
| D | IA64minstate.h | 192 st8.spill [r17]=rR1, 16; /* save original r1 */ \
194 .mem.offset 0, 0; st8.spill [r16]=r2, 16; \
195 .mem.offset 8, 0; st8.spill [r17]=r3, 16; \
198 .mem.offset 0, 0; st8.spill [r16]=r12, 16; \
199 .mem.offset 8, 0; st8.spill [r17]=r13, 16; \
203 .mem.offset 0, 0; st8.spill [r16]=r14, 16; \
204 .mem.offset 8, 0; st8.spill [r17]=r15, 16; \
207 .mem.offset 0, 0; st8.spill [r16]=r8, 16; \
208 .mem.offset 8, 0; st8.spill [r17]=r9, 16; \
212 .mem.offset 0, 0; st8.spill [r16]=r10, 16; \
[all …]
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| /external/libffi/src/ia64/ |
| D | unix.S | 308 stf.spill [r16] = f8, 32
309 stf.spill [r17] = f9, 32
312 stf.spill [r16] = f10, 32
313 stf.spill [r17] = f11, 32
315 stf.spill [r16] = f12, 32
316 stf.spill [r17] = f13, 32
318 stf.spill [r16] = f14, 32
319 stf.spill [r17] = f15, 24
322 st8.spill [r16] = in0, 16
324 st8.spill [r17] = in1, 16
[all …]
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| /external/chromium_org/v8/test/mjsunit/regress/ |
| D | regress-crbug-173907b.js | 36 %NeverOptimizeFunction(spill);
37 function spill() { function
45 spill(); // At this point initial values for phi1 and phi2 are spilled.
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| D | regress-crbug-173907.js | 36 function spill() { function
45 spill(); // At this point initial values for phi1 and phi2 are spilled.
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| /external/llvm/test/CodeGen/ARM/ |
| D | 2010-05-18-LocalAllocCrash.ll | 3 ;; This test would spill %R4 before the call to zz, but it forgot to move the
4 ; 'last use' marker to the spill.
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| D | crash-O0.ll | 7 ; This function would crash RegAllocFast because it tried to spill %CPSR.
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| D | gpr-paired-spill-thumbinst.ll | 17 ; Make sure we are actually creating the Thumb versions of the spill
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| /external/chromium_org/third_party/sqlite/src/test/ |
| D | tkt2409.test | 15 # obtain an EXCLUSIVE lock while trying to spill the cache during
23 # tkt-2409-1.*: Cause a cache-spill during an INSERT that is within
29 # an exclusive lock when attempting a cache-spill is no longer an
33 # tkt-2409-2.*: Cause a cache-spill while updating the change-counter
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| /external/llvm/test/CodeGen/Thumb2/ |
| D | aligned-spill.ll | 7 ; This function is forced to spill a double.
8 ; Verify that the spill slot is properly aligned.
33 ; Since the spill slot is only 8 bytes, technically it would be fine to only
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| D | inflate-regs.ll | 7 ; RAGreedy should split the range and use d16-d31 to avoid a spill.
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| /external/llvm/lib/CodeGen/ |
| D | Spiller.h | 30 virtual void spill(LiveRangeEdit &LRE) = 0;
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| D | RegAllocBasic.cpp | 207 spiller().spill(LRE); in spillInterferences()
266 spiller().spill(LRE); in selectOrSplit()
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| /external/llvm/lib/Target/X86/ |
| D | X86CompilationCallback_Win64.asm | 24 ; WARNING: We cannot use register spill area - we're generating stubs by hands!
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| /external/llvm/test/CodeGen/AArch64/ |
| D | tls-dynamic-together.ll | 4 ; glue) then LLVM will separate them quite happily (with a spill at O0, hence
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| /external/llvm/test/CodeGen/X86/ |
| D | 2011-10-11-SpillDead.ll | 7 ; The call to @g forces a spill of that register.
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| D | reghinting.ll | 4 ;; The registers %x and %y must both spill across the finit call.
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| D | 2008-01-08-SchedulerCrash.ll | 3 ; Test scheduling a multi-use compare. We should neither spill flags
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | vrspill.ll | 4 ; This verifies that we generate correct spill/reload code for vector regs.
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| D | buildvec_canonicalize.ll | 12 ; The fmul will spill a vspltisw to create a -0.0 vector used as the addend
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| D | frame-size.ll | 10 ; Check that the RS spill slot has been allocated (because the estimate
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcRegisterInfo.td | 152 // Register class for 64-bit mode, with a 64-bit spill slot size.
155 // spill slot is a stricter constraint than only requiring a 32-bit spill slot.
|
| /external/llvm/test/CodeGen/SystemZ/ |
| D | frame-18.ll | 5 ; We need to allocate a 4-byte spill slot, rounded to 8 bytes. The frame
51 ; Same for i64, except that the full spill slot is used.
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| D | frame-17.ll | 6 ; 4-byte spill slot, rounded to 8 bytes. The frame size should be exactly
71 ; Same for doubles, except that the full spill slot is used.
132 ; The long double case needs a 16-byte spill slot.
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| D | frame-13.ll | 21 ; emergency spill slots at 160(%r15), the amount that we need to allocate
206 ; Repeat f2 in a case that needs the emergency spill slots (because all
242 ; And again with maximum register pressure. The only spill slots that the
245 ; spill a second register. This leads to an extra displacement of 8.
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| /external/llvm/test/CodeGen/Thumb/ |
| D | 2011-06-16-NoGPRs.ll | 6 ; to spill them.
|