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Searched refs:urb_entry_read_offset (Results 1 – 25 of 26) sorted by relevance

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/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/
Dgen6_sf_state.c56 get_attr_override(struct brw_vue_map *vue_map, int urb_entry_read_offset, in get_attr_override() argument
91 int source_attr = slot - 2 * urb_entry_read_offset; in get_attr_override()
132 int urb_entry_read_offset = 1; in upload_sf_state() local
308 urb_entry_read_offset, attr, in upload_sf_state()
331 urb_entry_read_offset << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT; in upload_sf_state()
Dgen7_sol_state.c200 int urb_entry_read_offset = 0; in upload_3dstate_streamout() local
202 urb_entry_read_offset; in upload_3dstate_streamout()
221 dw2 |= urb_entry_read_offset << SO_STREAM_0_VERTEX_READ_OFFSET_SHIFT; in upload_3dstate_streamout()
Dgen7_sf_state.c44 int urb_entry_read_offset = 1; in upload_sbe_state() local
106 urb_entry_read_offset, attr, in upload_sbe_state()
124 urb_entry_read_offset << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT; in upload_sbe_state()
Dbrw_sf.c79 c.urb_entry_read_offset = brw_sf_compute_urb_entry_read_offset(intel); in compile_sf_prog()
80 c.nr_attr_regs = (c.vue_map.num_slots + 1)/2 - c.urb_entry_read_offset; in compile_sf_prog()
Dbrw_sf.h95 int urb_entry_read_offset; member
Dbrw_gs_state.c67 gs->thread3.urb_entry_read_offset = 0; in brw_upload_gs_unit()
Dbrw_clip_state.c67 clip->thread3.urb_entry_read_offset = 0; in brw_upload_clip_unit()
Dbrw_vs_state.c89 vs->thread3.urb_entry_read_offset = 0; in brw_upload_vs_unit()
Dbrw_sf_emit.c54 int vue_slot = (reg + c->urb_entry_read_offset) * 2 + half; in vert_reg_to_vert_result()
66 assert (vue_slot >= c->urb_entry_read_offset); in get_vert_result()
67 GLuint off = vue_slot / 2 - c->urb_entry_read_offset; in get_vert_result()
Dbrw_state.h234 get_attr_override(struct brw_vue_map *vue_map, int urb_entry_read_offset,
Dbrw_wm_state.c130 wm->thread3.urb_entry_read_offset = 0; in brw_upload_wm_unit()
Dbrw_sf_state.c167 sf->thread3.urb_entry_read_offset = in upload_sf_unit()
Dbrw_structs.h134 GLuint urb_entry_read_offset:6; member
/external/mesa3d/src/mesa/drivers/dri/i965/
Dgen6_sf_state.c56 get_attr_override(struct brw_vue_map *vue_map, int urb_entry_read_offset, in get_attr_override() argument
91 int source_attr = slot - 2 * urb_entry_read_offset; in get_attr_override()
132 int urb_entry_read_offset = 1; in upload_sf_state() local
308 urb_entry_read_offset, attr, in upload_sf_state()
331 urb_entry_read_offset << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT; in upload_sf_state()
Dgen7_sol_state.c200 int urb_entry_read_offset = 0; in upload_3dstate_streamout() local
202 urb_entry_read_offset; in upload_3dstate_streamout()
221 dw2 |= urb_entry_read_offset << SO_STREAM_0_VERTEX_READ_OFFSET_SHIFT; in upload_3dstate_streamout()
Dgen7_sf_state.c44 int urb_entry_read_offset = 1; in upload_sbe_state() local
106 urb_entry_read_offset, attr, in upload_sbe_state()
124 urb_entry_read_offset << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT; in upload_sbe_state()
Dbrw_sf.c79 c.urb_entry_read_offset = brw_sf_compute_urb_entry_read_offset(intel); in compile_sf_prog()
80 c.nr_attr_regs = (c.vue_map.num_slots + 1)/2 - c.urb_entry_read_offset; in compile_sf_prog()
Dbrw_sf.h95 int urb_entry_read_offset; member
Dbrw_gs_state.c67 gs->thread3.urb_entry_read_offset = 0; in brw_upload_gs_unit()
Dbrw_clip_state.c67 clip->thread3.urb_entry_read_offset = 0; in brw_upload_clip_unit()
Dbrw_vs_state.c89 vs->thread3.urb_entry_read_offset = 0; in brw_upload_vs_unit()
Dbrw_sf_emit.c54 int vue_slot = (reg + c->urb_entry_read_offset) * 2 + half; in vert_reg_to_vert_result()
66 assert (vue_slot >= c->urb_entry_read_offset); in get_vert_result()
67 GLuint off = vue_slot / 2 - c->urb_entry_read_offset; in get_vert_result()
Dbrw_state.h234 get_attr_override(struct brw_vue_map *vue_map, int urb_entry_read_offset,
Dbrw_wm_state.c130 wm->thread3.urb_entry_read_offset = 0; in brw_upload_wm_unit()
Dbrw_sf_state.c167 sf->thread3.urb_entry_read_offset = in upload_sf_unit()

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