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Searched refs:ImmR (Results 1 – 6 of 6) sorted by relevance

/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp477 unsigned ImmR = fieldFromInstruction(Insn, 16, 6); in DecodeBitfieldInstruction() local
487 if (ImmR > 31 || ImmS > 31) in DecodeBitfieldInstruction()
510 if (Opc == SBFM && ImmR == 0) { in DecodeBitfieldInstruction()
513 } else if (Opc == UBFM && ImmR == 0) { in DecodeBitfieldInstruction()
520 if (SF && (ImmS + 1) % 64 == ImmR) { in DecodeBitfieldInstruction()
524 } else if (!SF && (ImmS + 1) % 32 == ImmR) { in DecodeBitfieldInstruction()
551 Inst.addOperand(MCOperand::CreateImm(ImmR)); in DecodeBitfieldInstruction()
555 if (ImmS < ImmR) in DecodeBitfieldInstruction()
/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp145 unsigned ImmR = ImmROp.getImm(); in printBFXWidthOperand() local
148 assert(ImmS >= ImmR && "Invalid ImmR, ImmS combination for bitfield extract"); in printBFXWidthOperand()
150 O << '#' << (ImmS - ImmR + 1); in printBFXWidthOperand()
/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.cpp1004 uint32_t ImmR = RepeatWidth - Rotation; in isLogicalImm() local
1015 Bits = ImmS | (ImmR << 6) | (N << 12); in isLogicalImm()
1024 uint32_t ImmR = (Bits >> 6) & 0x3f; in isLogicalImmBits() local
1054 int Rotation = (ImmR & (Width - 1)); in isLogicalImmBits()
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td118 // (A64[SU]BFX Field, ImmR, ImmS).
120 // Note that ImmR and ImmS are already encoded for the actual instructions. The
121 // more natural LSB and Width mix together to form ImmR and ImmS, something
1032 (ins GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
1033 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1039 (ins GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
1040 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1053 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
1054 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1061 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
[all …]
DAArch64InstrFormats.td203 bits<6> ImmR;
210 let Inst{21-16} = ImmR;
819 bits<6> ImmR;
822 // N, ImmR and ImmS have no separate existence in any assembly syntax (or for
826 // ImmR = Imm{11-6};
/external/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp1839 int64_t ImmR = Inst.getOperand(ImmOps).getImm(); in validateInstruction() local
1842 if (ImmR != 0 && ImmS >= ImmR) { in validateInstruction()
1855 int64_t ImmR = Inst.getOperand(ImmOps).getImm(); in validateInstruction() local
1867 if (ImmS >= RegWidth || ImmS < ImmR) { in validateInstruction()