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Searched refs:R_SS (Results 1 – 11 of 11) sorted by relevance

/external/qemu/target-i386/
Dop_helper.c243 } else if (seg_reg == R_SS) { in tss_load_seg()
266 if (seg_reg == R_SS || seg_reg == R_CS) in tss_load_seg()
495 tss_load_seg(R_SS, new_segs[R_SS]); in switch_tss()
695 if (env->segs[R_SS].flags & DESC_B_MASK) in do_interrupt_protected()
700 ssp = env->segs[R_SS].base + esp; in do_interrupt_protected()
765 sp_mask = get_sp_mask(env->segs[R_SS].flags); in do_interrupt_protected()
766 ssp = env->segs[R_SS].base; in do_interrupt_protected()
794 PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector); in do_interrupt_protected()
811 PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector); in do_interrupt_protected()
830 cpu_x86_load_seg_cache(env, R_SS, ss, in do_interrupt_protected()
[all …]
Dhax-all.c730 get_seg(&env->segs[R_SS], &sregs->_ss); in hax_get_segments()
749 set_v8086_seg(&sregs->_ss, &env->segs[R_SS]); in hax_set_segments()
756 set_seg(&sregs->_ss, &env->segs[R_SS]); in hax_set_segments()
807 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> in hax_setup_qemu_emulator()
816 env->segs[R_SS].base) != 0) << in hax_setup_qemu_emulator()
Dkvm.c401 set_v8086_seg(&sregs.ss, &env->segs[R_SS]); in kvm_put_sregs()
408 set_seg(&sregs.ss, &env->segs[R_SS]); in kvm_put_sregs()
515 get_seg(&env->segs[R_SS], &sregs.ss); in kvm_get_sregs()
560 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> in kvm_get_sregs()
569 env->segs[R_SS].base) != 0) << in kvm_get_sregs()
Dcpu.h71 #define R_SS 2 macro
748 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) in cpu_x86_load_seg_cache()
764 env->segs[R_SS].base) != 0) << in cpu_x86_load_seg_cache()
Dtranslate.c2062 override = R_SS; in gen_lea_modrm()
2135 override = R_SS; in gen_lea_modrm()
2401 if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS)) in gen_movl_seg_T0()
2405 if (seg_reg == R_SS) in gen_movl_seg_T0()
2474 gen_op_addl_A0_seg(R_SS); in gen_push_T0()
2479 gen_op_addl_A0_seg(R_SS); in gen_push_T0()
2514 gen_op_addl_A0_seg(R_SS); in gen_push_T1()
2518 gen_op_addl_A0_seg(R_SS); in gen_push_T1()
2542 gen_op_addl_A0_seg(R_SS); in gen_pop_T0()
2545 gen_op_addl_A0_seg(R_SS); in gen_pop_T0()
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Dhelper.c508 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, in cpu_reset()
/external/qemu/
Dkqemu.c531 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc, in do_syscall()
552 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc, in do_syscall()
835 new_hflags |= (env->segs[R_SS].flags & DESC_B_MASK) in kqemu_cpu_exec()
849 env->segs[R_SS].base) != 0) << in kqemu_cpu_exec()
Dgdbstub.c540 case 3: GET_REG32(env->segs[R_SS].selector); in cpu_gdb_read_register()
599 case 3: LOAD_SEG(11, R_SS); return 4; in cpu_gdb_write_register()
Dmonitor.c1884 SEG("ss", R_SS)
/external/valgrind/main/VEX/priv/
Dguest_x86_toIR.c309 #define R_SS 2 macro
492 case R_SS: return OFFB_SS; in segmentGuestRegOffset()
1293 case R_SS: return "%ss"; in nameSReg()
13801 dis_pop_segreg( R_SS, sz ); break; in disInstr_X86_WRK()
13942 dis_push_segreg( R_SS, sz ); break; in disInstr_X86_WRK()
Dguest_amd64_toIR.c472 #define R_SS 2 macro