1 //===-- HexagonBaseInfo.h - Top level definitions for Hexagon --*- C++ -*--===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains small standalone helper functions and enum definitions for 11 // the Hexagon target useful for the compiler back-end and the MC libraries. 12 // As such, it deliberately does not include references to LLVM core 13 // code gen types, passes, etc.. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #ifndef HEXAGONBASEINFO_H 18 #define HEXAGONBASEINFO_H 19 20 #include "HexagonMCTargetDesc.h" 21 #include "llvm/Support/ErrorHandling.h" 22 23 namespace llvm { 24 25 /// HexagonII - This namespace holds all of the target specific flags that 26 /// instruction info tracks. 27 /// 28 namespace HexagonII { 29 // *** The code below must match HexagonInstrFormat*.td *** // 30 31 // Insn types. 32 // *** Must match HexagonInstrFormat*.td *** 33 enum Type { 34 TypePSEUDO = 0, 35 TypeALU32 = 1, 36 TypeCR = 2, 37 TypeJR = 3, 38 TypeJ = 4, 39 TypeLD = 5, 40 TypeST = 6, 41 TypeSYSTEM = 7, 42 TypeXTYPE = 8, 43 TypeMEMOP = 9, 44 TypeNV = 10, 45 TypePREFIX = 30, // Such as extenders. 46 TypeENDLOOP = 31 // Such as end of a HW loop. 47 }; 48 49 enum SubTarget { 50 HasV2SubT = 0xf, 51 HasV2SubTOnly = 0x1, 52 NoV2SubT = 0x0, 53 HasV3SubT = 0xe, 54 HasV3SubTOnly = 0x2, 55 NoV3SubT = 0x1, 56 HasV4SubT = 0xc, 57 NoV4SubT = 0x3, 58 HasV5SubT = 0x8, 59 NoV5SubT = 0x7 60 }; 61 62 enum AddrMode { 63 NoAddrMode = 0, // No addressing mode 64 Absolute = 1, // Absolute addressing mode 65 AbsoluteSet = 2, // Absolute set addressing mode 66 BaseImmOffset = 3, // Indirect with offset 67 BaseLongOffset = 4, // Indirect with long offset 68 BaseRegOffset = 5, // Indirect with register offset 69 PostInc = 6 // Post increment addressing mode 70 }; 71 72 enum MemAccessSize { 73 NoMemAccess = 0, // Not a memory acces instruction. 74 ByteAccess = 1, // Byte access instruction (memb). 75 HalfWordAccess = 2, // Half word access instruction (memh). 76 WordAccess = 3, // Word access instrution (memw). 77 DoubleWordAccess = 4 // Double word access instruction (memd) 78 }; 79 80 // MCInstrDesc TSFlags 81 // *** Must match HexagonInstrFormat*.td *** 82 enum { 83 // This 5-bit field describes the insn type. 84 TypePos = 0, 85 TypeMask = 0x1f, 86 87 // Solo instructions. 88 SoloPos = 5, 89 SoloMask = 0x1, 90 91 // Predicated instructions. 92 PredicatedPos = 6, 93 PredicatedMask = 0x1, 94 PredicatedFalsePos = 7, 95 PredicatedFalseMask = 0x1, 96 PredicatedNewPos = 8, 97 PredicatedNewMask = 0x1, 98 99 // New-Value consumer instructions. 100 NewValuePos = 9, 101 NewValueMask = 0x1, 102 103 // New-Value producer instructions. 104 hasNewValuePos = 10, 105 hasNewValueMask = 0x1, 106 107 // Which operand consumes or produces a new value. 108 NewValueOpPos = 11, 109 NewValueOpMask = 0x7, 110 111 // Which bits encode the new value. 112 NewValueBitsPos = 14, 113 NewValueBitsMask = 0x3, 114 115 // Stores that can become new-value stores. 116 mayNVStorePos = 16, 117 mayNVStoreMask = 0x1, 118 119 // New-value store instructions. 120 NVStorePos = 17, 121 NVStoreMask = 0x1, 122 123 // Extendable insns. 124 ExtendablePos = 18, 125 ExtendableMask = 0x1, 126 127 // Insns must be extended. 128 ExtendedPos = 19, 129 ExtendedMask = 0x1, 130 131 // Which operand may be extended. 132 ExtendableOpPos = 20, 133 ExtendableOpMask = 0x7, 134 135 // Signed or unsigned range. 136 ExtentSignedPos = 23, 137 ExtentSignedMask = 0x1, 138 139 // Number of bits of range before extending operand. 140 ExtentBitsPos = 24, 141 ExtentBitsMask = 0x1f, 142 143 // Valid subtargets 144 validSubTargetPos = 29, 145 validSubTargetMask = 0xf, 146 147 // Addressing mode for load/store instructions. 148 AddrModePos = 33, 149 AddrModeMask = 0x7, 150 151 // Access size of memory access instructions (load/store). 152 MemAccessSizePos = 36, 153 MemAccesSizeMask = 0x7 154 }; 155 156 // *** The code above must match HexagonInstrFormat*.td *** // 157 158 // Hexagon specific MO operand flag mask. 159 enum HexagonMOTargetFlagVal { 160 //===------------------------------------------------------------------===// 161 // Hexagon Specific MachineOperand flags. 162 MO_NO_FLAG, 163 164 HMOTF_ConstExtended = 1, 165 166 /// MO_PCREL - On a symbol operand, indicates a PC-relative relocation 167 /// Used for computing a global address for PIC compilations 168 MO_PCREL, 169 170 /// MO_GOT - Indicates a GOT-relative relocation 171 MO_GOT, 172 173 // Low or high part of a symbol. 174 MO_LO16, MO_HI16, 175 176 // Offset from the base of the SDA. 177 MO_GPREL 178 }; 179 180 } // End namespace HexagonII. 181 182 } // End namespace llvm. 183 184 #endif 185