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1//===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//==-----------------------------------------------------------------------===//
9
10// Include AMDIL TD files
11include "AMDILBase.td"
12
13//===----------------------------------------------------------------------===//
14// Subtarget Features
15//===----------------------------------------------------------------------===//
16
17// Debugging Features
18
19def FeatureDumpCode : SubtargetFeature <"DumpCode",
20        "DumpCode",
21        "true",
22        "Dump MachineInstrs in the CodeEmitter">;
23
24// Target features
25
26def FeatureFP64     : SubtargetFeature<"fp64",
27        "FP64",
28        "true",
29        "Enable 64bit double precision operations">;
30
31def Feature64BitPtr : SubtargetFeature<"64BitPtr",
32        "Is64bit",
33        "true",
34        "Specify if 64bit addressing should be used.">;
35
36def Feature32on64BitPtr : SubtargetFeature<"64on32BitPtr",
37        "Is32on64bit",
38        "false",
39        "Specify if 64bit sized pointers with 32bit addressing should be used.">;
40
41def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
42        "R600ALUInst",
43        "false",
44        "Older version of ALU instructions encoding.">;
45
46def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
47        "HasVertexCache",
48        "true",
49        "Specify use of dedicated vertex cache.">;
50
51def FeatureCaymanISA : SubtargetFeature<"caymanISA",
52        "CaymanISA",
53        "true",
54        "Use Cayman ISA">;
55
56class SubtargetFeatureFetchLimit <string Value> :
57                          SubtargetFeature <"fetch"#Value,
58        "TexVTXClauseSize",
59        Value,
60        "Limit the maximum number of fetches in a clause to "#Value>;
61
62def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
63def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
64
65class SubtargetFeatureGeneration <string Value,
66                                  list<SubtargetFeature> Implies> :
67        SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
68                          Value#" GPU generation", Implies>;
69
70def FeatureR600 : SubtargetFeatureGeneration<"R600",
71        [FeatureR600ALUInst, FeatureFetchLimit8]>;
72
73def FeatureR700 : SubtargetFeatureGeneration<"R700",
74        [FeatureFetchLimit16]>;
75
76def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
77        [FeatureFetchLimit16]>;
78
79def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
80        [FeatureFetchLimit16]>;
81
82def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
83        [Feature64BitPtr, FeatureFP64]>;
84
85//===----------------------------------------------------------------------===//
86
87def AMDGPUInstrInfo : InstrInfo {
88  let guessInstructionProperties = 1;
89}
90
91//===----------------------------------------------------------------------===//
92// Declare the target which we are implementing
93//===----------------------------------------------------------------------===//
94def AMDGPUAsmWriter : AsmWriter {
95    string AsmWriterClassName = "InstPrinter";
96    int Variant = 0;
97    bit isMCAsmWriter = 1;
98}
99
100def AMDGPU : Target {
101  // Pull in Instruction Info:
102  let InstructionSet = AMDGPUInstrInfo;
103  let AssemblyWriters = [AMDGPUAsmWriter];
104}
105
106// Include AMDGPU TD files
107include "R600Schedule.td"
108include "SISchedule.td"
109include "Processors.td"
110include "AMDGPUInstrInfo.td"
111include "AMDGPUIntrinsics.td"
112include "AMDGPURegisterInfo.td"
113include "AMDGPUInstructions.td"
114include "AMDGPUCallingConv.td"
115