# loongson2 Events
#
event:0x00 counters:0 um:zero minimum:10000 name:CPU_CLK_UNHALTED : Cycles outside of haltstate
event:0x01 counters:0 um:zero minimum:5000 name:BRANCH_INSTRUCTIONS : Branch instructions
event:0x02 counters:0 um:zero minimum:400 name:JUMP_INSTRUCTIONS : JR instructions
event:0x03 counters:0 um:zero minimum:500 name:JR31_INSTRUCTIONS : JR(rs=31) instructions
event:0x04 counters:0 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses
event:0x05 counters:0 um:zero minimum:500 name:ALU1_ISSUED : ALU1 operation issued
event:0x06 counters:0 um:zero minimum:8000 name:MEM_ISSUED : Memory read/write issued
event:0x07 counters:0 um:zero minimum:300 name:FALU1_ISSUED : Float ALU1 operation issued
event:0x08 counters:0 um:zero minimum:200 name:BHT_BRANCH_INSTRUCTIONS : BHT prediction instructions
event:0x09 counters:0 um:zero minimum:200 name:MEM_READ : Read from primary memory
event:0x0a counters:0 um:zero minimum:300 name:FQUEUE_FULL : Fix queue full
event:0x0b counters:0 um:zero minimum:300 name:ROQ_FULL : Reorder queue full
event:0x0c counters:0 um:zero minimum:300 name:CP0_QUEUE_FULL : CP0 queue full
event:0x0d counters:0 um:zero minimum:300 name:TLB_REFILL : TLB refill exception
event:0x0e counters:0 um:zero minimum:5 name:EXCEPTION : Exceptions
event:0x0f counters:0 um:zero minimum:300 name:INTERNAL_EXCEPTION : Internal exceptions
event:0x10 counters:1 um:zero minimum:5000 name:INSTRUCTION_COMMITTED : Instruction committed 
event:0x11 counters:1 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branch mispredicted
event:0x12 counters:1 um:zero minimum:200 name:JR_MISPREDICTED : JR mispredicted
event:0x13 counters:1 um:zero minimum:200 name:JR31_MISPREDICTED : JR31 mispredicted
event:0x14 counters:1 um:zero minimum:500 name:DCACHE_MISSES : Data cache misses
event:0x15 counters:1 um:zero minimum:500 name:ALU2_ISSUED : ALU2 operation issued
event:0x16 counters:1 um:zero minimum:500 name:FALU2_ISSUED : FALU2 operation issued
event:0x17 counters:1 um:zero minimum:500 name:UNCACHED_ACCESS : Uncached accesses
event:0x18 counters:1 um:zero minimum:500 name:BHT_MISPREDICTED : Branch history table mispredicted
event:0x19 counters:1 um:zero minimum:5000 name:MEM_WRITE : Write to memory
event:0x1a counters:1 um:zero minimum:500 name:FTQ_FULL : Float queue full
event:0x1b counters:1 um:zero minimum:500 name:BRANCH_QUEUE_FULL : Branch queue full
event:0x1c counters:1 um:zero minimum:500 name:ITLB_MISSES : Instruction TLB misses
event:0x1d counters:1 um:zero minimum:500 name:TOTAL_EXCEPTIONS : Total exceptions
event:0x1e counters:1 um:zero minimum:500 name:LOAD_SPECULATION_MISSES : Load speculation misses
event:0x1f counters:1 um:zero minimum:500 name:CP0Q_FORWARD_VALID : CP0 queue forward valid