1685   switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) {  in GenMachineSpecificExtendedMethodMIR()
1743   int num_vector_reg = mir->dalvikInsn.vA;  in ReserveVectorRegisters()
1786   int type_size = mir->dalvikInsn.vB;  in GenConst128()
1789   RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenConst128()
1790   uint32_t *args = mir->dalvikInsn.arg;  in GenConst128()
1829   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);  in GenMoveVector()
1830   RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenMoveVector()
1831   RegStorage rs_src = RegStorage::Solo128(mir->dalvikInsn.vB);  in GenMoveVector()
1837   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenMultiplyVectorSignedByte()
1838   RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);  in GenMultiplyVectorSignedByte()
1878   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);  in GenMultiplyVector()
1879   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);  in GenMultiplyVector()
1880   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenMultiplyVector()
1881   RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);  in GenMultiplyVector()
1908   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);  in GenAddVector()
1909   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);  in GenAddVector()
1910   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenAddVector()
1911   RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);  in GenAddVector()
1939   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);  in GenSubtractVector()
1940   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);  in GenSubtractVector()
1941   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenSubtractVector()
1942   RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);  in GenSubtractVector()
1970   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenShiftByteVector()
1974   int imm = mir->dalvikInsn.vB;  in GenShiftByteVector()
1976   switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) {  in GenShiftByteVector()
2019   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);  in GenShiftLeftVector()
2020   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);  in GenShiftLeftVector()
2021   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenShiftLeftVector()
2022   int imm = mir->dalvikInsn.vB;  in GenShiftLeftVector()
2047   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);  in GenSignedShiftRightVector()
2048   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);  in GenSignedShiftRightVector()
2049   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenSignedShiftRightVector()
2050   int imm = mir->dalvikInsn.vB;  in GenSignedShiftRightVector()
2072   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);  in GenUnsignedShiftRightVector()
2073   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);  in GenUnsignedShiftRightVector()
2074   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenUnsignedShiftRightVector()
2075   int imm = mir->dalvikInsn.vB;  in GenUnsignedShiftRightVector()
2101   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);  in GenAndVector()
2102   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenAndVector()
2103   RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);  in GenAndVector()
2109   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);  in GenOrVector()
2110   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenOrVector()
2111   RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);  in GenOrVector()
2117   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);  in GenXorVector()
2118   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenXorVector()
2119   RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);  in GenXorVector()
2131   const_mirp->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpConstVector);  in MaskVectorRegister()
2132   const_mirp->dalvikInsn.arg[0] = m0;  in MaskVectorRegister()
2133   const_mirp->dalvikInsn.arg[1] = m1;  in MaskVectorRegister()
2134   const_mirp->dalvikInsn.arg[2] = m2;  in MaskVectorRegister()
2135   const_mirp->dalvikInsn.arg[3] = m3;  in MaskVectorRegister()
2142   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);  in GenAddReduceVector()
2143   RegStorage rs_src1 = RegStorage::Solo128(mir->dalvikInsn.vB);  in GenAddReduceVector()
2147   int vec_bytes = (mir->dalvikInsn.vC & 0xFFFF) / 8;  in GenAddReduceVector()
2235   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);  in GenReduceVector()
2237   RegStorage rs_src1 = RegStorage::Solo128(mir->dalvikInsn.vB);  in GenReduceVector()
2238   int extract_index = mir->dalvikInsn.arg[0];  in GenReduceVector()
2275   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);  in GenSetVector()
2276   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);  in GenSetVector()
2277   RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenSetVector()
2348   int *args = reinterpret_cast<int*>(mir->dalvikInsn.arg);  in ScanVectorLiteral()
2360   int *args = reinterpret_cast<int*>(mir->dalvikInsn.arg);  in AddVectorLiteral()