Lines Matching refs:dd

467   virtual void vmovd(DRegister dd, DRegister dm, Condition cond = AL) = 0;
471   virtual bool vmovd(DRegister dd, double d_imm, Condition cond = AL) = 0;
475   virtual void vldrd(DRegister dd, const Address& ad, Condition cond = AL) = 0;
476   virtual void vstrd(DRegister dd, const Address& ad, Condition cond = AL) = 0;
479   virtual void vaddd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) = 0;
481   virtual void vsubd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) = 0;
483   virtual void vmuld(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) = 0;
485   virtual void vmlad(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) = 0;
487   virtual void vmlsd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) = 0;
489   virtual void vdivd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) = 0;
492   virtual void vabsd(DRegister dd, DRegister dm, Condition cond = AL) = 0;
494   virtual void vnegd(DRegister dd, DRegister dm, Condition cond = AL) = 0;
496   virtual void vsqrtd(DRegister dd, DRegister dm, Condition cond = AL) = 0;
499   virtual void vcvtds(DRegister dd, SRegister sm, Condition cond = AL) = 0;
503   virtual void vcvtdi(DRegister dd, SRegister sm, Condition cond = AL) = 0;
507   virtual void vcvtdu(DRegister dd, SRegister sm, Condition cond = AL) = 0;
510   virtual void vcmpd(DRegister dd, DRegister dm, Condition cond = AL) = 0;
512   virtual void vcmpdz(DRegister dd, Condition cond = AL) = 0;
543   virtual void LoadDImmediate(DRegister dd, double value,