367   SUnit *PredSU = PredEdge->getSUnit();  in ReleasePred()  local
370   if (PredSU->NumSuccsLeft == 0) {  in ReleasePred()
372     PredSU->dump(this);  in ReleasePred()
377   --PredSU->NumSuccsLeft;  in ReleasePred()
382     PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge->getLatency());  in ReleasePred()
387   if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {  in ReleasePred()
388     PredSU->isAvailable = true;  in ReleasePred()
390     unsigned Height = PredSU->getHeight();  in ReleasePred()
394     if (isReady(PredSU)) {  in ReleasePred()
395       AvailableQueue->push(PredSU);  in ReleasePred()
399     else if (!PredSU->isPending) {  in ReleasePred()
400       PredSU->isPending = true;  in ReleasePred()
401       PendingQueue.push_back(PredSU);  in ReleasePred()
793   SUnit *PredSU = PredEdge->getSUnit();  in CapturePred()  local
794   if (PredSU->isAvailable) {  in CapturePred()
795     PredSU->isAvailable = false;  in CapturePred()
796     if (!PredSU->isPending)  in CapturePred()
797       AvailableQueue->remove(PredSU);  in CapturePred()
800   assert(PredSU->NumSuccsLeft < UINT_MAX && "NumSuccsLeft will overflow!");  in CapturePred()
801   ++PredSU->NumSuccsLeft;  in CapturePred()
1844     SUnit *PredSU = I->getSUnit();  in CalcNodeSethiUllmanNumber()  local
1845     unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU, SUNumbers);  in CalcNodeSethiUllmanNumber()
1947     SUnit *PredSU = I->getSUnit();  in HighRegPressure()  local
1950     if (PredSU->NumRegDefsLeft == 0) {  in HighRegPressure()
1953     for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);  in HighRegPressure()
1997     SUnit *PredSU = I->getSUnit();  in RegPressureDiff()  local
2000     if (PredSU->NumRegDefsLeft == 0) {  in RegPressureDiff()
2001       if (PredSU->getNode()->isMachineOpcode())  in RegPressureDiff()
2005     for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);  in RegPressureDiff()
2041     SUnit *PredSU = I->getSUnit();  in scheduledNode()  local
2044     if (PredSU->NumRegDefsLeft == 0) {  in scheduledNode()
2062     --PredSU->NumRegDefsLeft;  in scheduledNode()
2063     unsigned SkipRegDefs = PredSU->NumRegDefsLeft;  in scheduledNode()
2064     for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);  in scheduledNode()
2123     SUnit *PredSU = I->getSUnit();  in unscheduledNode()  local
2126     if (PredSU->NumSuccsLeft != PredSU->Succs.size())  in unscheduledNode()
2128     const SDNode *PN = PredSU->getNode();  in unscheduledNode()
2222     const SUnit *PredSU = I->getSUnit();  in hasOnlyLiveInOpers()  local
2223     if (PredSU->getNode() &&  in hasOnlyLiveInOpers()
2224         PredSU->getNode()->getOpcode() == ISD::CopyFromReg) {  in hasOnlyLiveInOpers()
2226         cast<RegisterSDNode>(PredSU->getNode()->getOperand(1))->getReg();  in hasOnlyLiveInOpers()
2296     SUnit *PredSU = I->getSUnit();  in resetVRegCycle()  local
2297     if (PredSU->isVRegCycle) {  in resetVRegCycle()
2298       assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg &&  in resetVRegCycle()
2829     SUnit *PredSU = nullptr;  in PrescheduleNodesWithMultipleUses()  local
2833         PredSU = II->getSUnit();  in PrescheduleNodesWithMultipleUses()
2836     assert(PredSU);  in PrescheduleNodesWithMultipleUses()
2840     if (PredSU->hasPhysRegDefs)  in PrescheduleNodesWithMultipleUses()
2843     if (PredSU->NumSuccs == 1)  in PrescheduleNodesWithMultipleUses()
2854     for (SUnit::const_succ_iterator II = PredSU->Succs.begin(),  in PrescheduleNodesWithMultipleUses()
2855          EE = PredSU->Succs.end(); II != EE; ++II) {  in PrescheduleNodesWithMultipleUses()
2874                  << " next to PredSU #" << PredSU->NodeNum  in PrescheduleNodesWithMultipleUses()
2876     for (unsigned i = 0; i != PredSU->Succs.size(); ++i) {  in PrescheduleNodesWithMultipleUses()
2877       SDep Edge = PredSU->Succs[i];  in PrescheduleNodesWithMultipleUses()
2881         Edge.setSUnit(PredSU);  in PrescheduleNodesWithMultipleUses()