1234     if (Subtarget->hasInt256()) {  in resetOperationActions()
1698         if (Subtarget->hasInt256())  in getOptimalMemOpType()
3763       (VT.is256BitVector() && !Subtarget->hasInt256()))  in isPALIGNRMask()
4907     if (Subtarget->hasInt256()) { // AVX2  in getZeroVector()
5801         if (!Subtarget->hasInt256())  in LowerVectorBroadcast()
5833   if (ConstSplatVal && Subtarget->hasInt256()) {  in LowerVectorBroadcast()
5862   if (!IsLoad && Subtarget->hasInt256() &&  in LowerVectorBroadcast()
5875   if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {  in LowerVectorBroadcast()
6524     if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))  in LowerBUILD_VECTOR()
6528       return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);  in LowerBUILD_VECTOR()
8016                         bool hasInt256, unsigned *MaskOut = nullptr) {  in isBlendMask()  argument
8025   if (!hasInt256 && VT == MVT::v16i16)  in isBlendMask()
8067                      Subtarget->hasInt256() && "Trying to lower a "  in LowerVECTOR_SHUFFLEtoBlend()
8078   if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {  in LowerVECTOR_SHUFFLEtoBlend()
8551   if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||  in LowerVECTOR_SHUFFLEv32i8()
9115   if (!Subtarget->hasInt256() && VT.is256BitVector())  in LowerVectorIntExtend()
9262   bool HasInt256   = Subtarget->hasInt256();  in LowerVECTOR_SHUFFLE()
9488   if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),  in LowerVECTOR_SHUFFLE()
9567   if (VT == MVT::v16i16 && Subtarget->hasInt256()) {  in LowerVECTOR_SHUFFLE()
9651   if (!Subtarget->hasInt256() && VT == MVT::v16i16)  in LowerVSELECTtoBlend()
9665   if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {  in LowerVSELECTtoBlend()
9808         (VecVT.is256BitVector() && Subtarget->hasInt256() &&  in LowerEXTRACT_VECTOR_ELT()
11097   if (Subtarget->hasInt256())  in LowerAVXExtend()
11225     if (Subtarget->hasInt256()) {  in LowerTRUNCATE()
11246     if (Subtarget->hasInt256()) {  in LowerTRUNCATE()
12207   if (VT.is256BitVector() && !Subtarget->hasInt256())  in LowerVSETCC()
12770   if (Subtarget->hasInt256())  in LowerSIGN_EXTEND()
15032   if (VT.is256BitVector() && !Subtarget->hasInt256())  in LowerMUL()
15157          (VT == MVT::v8i32 && Subtarget->hasInt256()));  in LowerMUL_LOHI()
15219           (Subtarget->hasInt256() &&  in LowerScalarImmediateShift()
15280       if (Subtarget->hasInt256() && VT == MVT::v32i8) {  in LowerScalarImmediateShift()
15330       (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&  in LowerScalarImmediateShift()
15386       (Subtarget->hasInt256() &&  in LowerScalarVariableShift()
15491       (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||  in LowerScalarVariableShift()
15543   if (Subtarget->hasInt256()) {  in LowerShift()
15561        (Subtarget->hasInt256() && VT == MVT::v16i16)) &&  in LowerShift()
15718   if (Subtarget->hasInt256() && VT == MVT::v8i16) {  in LowerShift()
15861       if (!Subtarget->hasInt256()) {  in LowerSIGN_EXTEND_INREG()
16708   if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))  in isVectorShiftByScalarCheap()
16834       (SVT.is256BitVector() && Subtarget->hasInt256())) {  in isShuffleMaskLegal()
16853           isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||  in isShuffleMaskLegal()
16854           isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||  in isShuffleMaskLegal()
16856           isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||  in isShuffleMaskLegal()
16857           isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||  in isShuffleMaskLegal()
16858           isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||  in isShuffleMaskLegal()
16859           isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||  in isShuffleMaskLegal()
16860           isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));  in isShuffleMaskLegal()
19187   if (!Subtarget->hasInt256() && VT == MVT::v16i16)  in TransformVSELECTtoBlendVECTOR_SHUFFLE()
20295       (!Subtarget->hasInt256() ||  in performShiftToAllZeros()
20630         (VT == MVT::v4i64 && !Subtarget->hasInt256()))  in PerformOrCombine()
20839   if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&  in PerformLOADCombine()
20885     if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())  in PerformLOADCombine()
21035   if (VT.is256BitVector() && !Subtarget->hasInt256() &&  in PerformSTORECombine()
21522     if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())  in PerformSIGN_EXTEND_INREGCombine()
21911        (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&  in PerformAddCombine()
21944        (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&  in PerformSubCombine()