217   X86ScalarSSEf64 = Subtarget->hasSSE2();  in X86TargetLowering()
940   if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {  in resetOperationActions()
1115   if (Subtarget->hasSSE2()) {  in resetOperationActions()
1703       if (Subtarget->hasSSE2())  in getOptimalMemOpType()
1709                Subtarget->hasSSE2()) {  in getOptimalMemOpType()
1916         (Subtarget->is64Bit() && !Subtarget->hasSSE2()))  in LowerReturn()
1942           if (!Subtarget->hasSSE2())  in LowerReturn()
4899     if (Subtarget->hasSSE2()) {  // SSE2  in getZeroVector()
6523   if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {  in LowerBUILD_VECTOR()
8322     if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {  in LowerVECTOR_SHUFFLEv8i16()
8346     if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {  in LowerVECTOR_SHUFFLEv8i16()
9224   } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {  in NormalizeVectorShuffle()
9260   bool HasSSE2 = Subtarget->hasSSE2();  in LowerVECTOR_SHUFFLE()
12256     || (Subtarget->hasSSE2()  && (VET == MVT::i8));  in LowerVSETCC()
12268   bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);  in LowerVSETCC()
12309       assert(Subtarget->hasSSE2() && "Don't know how to lower!");  in LowerVSETCC()
12353       assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");  in LowerVSETCC()
12521       ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||  in LowerSELECT()
15040     assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&  in LowerMUL()
15156   assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||  in LowerMUL_LOHI()
15530   assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");  in LowerShift()
15673     assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");  in LowerShift()
15849   if (!Subtarget->hasSSE2() || !VT.isVector())  in LowerSIGN_EXTEND_INREG()
15933     if (Subtarget->hasSSE2() || Subtarget->is64Bit())  in LowerATOMIC_FENCE()
16002     assert(Subtarget->hasSSE2() && "Requires at least SSE2!");  in LowerBITCAST()
16031   assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&  in LowerBITCAST()
16328     assert(Subtarget->hasSSE2() && "Requires at least SSE2!");  in ReplaceNodeResults()
16444     assert(Subtarget->hasSSE2() && "Requires at least SSE2!");  in ReplaceNodeResults()
19110     if (!Subtarget->hasSSE2())  in matchIntegerMINMAX()
19116                      (Subtarget->hasSSE2() && VT == MVT::v16i8);  in matchIntegerMINMAX()
19118                    (Subtarget->hasSSE2() && VT == MVT::v8i16);  in matchIntegerMINMAX()
19228       (Subtarget->hasSSE2() ||  in PerformSELECTCombine()
19513       ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||  in PerformSELECTCombine()
19647         (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {  in PerformSELECTCombine()
19676       if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {  in PerformSELECTCombine()
20345   if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {  in CMPEQCombine()
20876   if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&  in PerformLOADCombine()
21151                      && Subtarget->hasSSE2();  in PerformSTORECombine()
22407     if (Subtarget->hasSSE2())  in LowerXConstraint()
22615       if (!Subtarget->hasSSE2()) break;  in getRegForInlineAsmConstraint()