1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains code to lower X86 MachineInstrs to their corresponding
11 // MCInst records.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "X86AsmPrinter.h"
16 #include "X86RegisterInfo.h"
17 #include "InstPrinter/X86ATTInstPrinter.h"
18 #include "MCTargetDesc/X86BaseInfo.h"
19 #include "llvm/ADT/SmallString.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
22 #include "llvm/CodeGen/StackMaps.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/IR/GlobalValue.h"
25 #include "llvm/IR/Mangler.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/MC/MCContext.h"
28 #include "llvm/MC/MCExpr.h"
29 #include "llvm/MC/MCInst.h"
30 #include "llvm/MC/MCInstBuilder.h"
31 #include "llvm/MC/MCStreamer.h"
32 #include "llvm/MC/MCSymbol.h"
33 using namespace llvm;
34
35 namespace {
36
37 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
38 class X86MCInstLower {
39 MCContext &Ctx;
40 const MachineFunction &MF;
41 const TargetMachine &TM;
42 const MCAsmInfo &MAI;
43 X86AsmPrinter &AsmPrinter;
44 public:
45 X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
46
47 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
48
49 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
50 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
51
52 private:
53 MachineModuleInfoMachO &getMachOMMI() const;
getMang() const54 Mangler *getMang() const {
55 return AsmPrinter.Mang;
56 }
57 };
58
59 } // end anonymous namespace
60
X86MCInstLower(const MachineFunction & mf,X86AsmPrinter & asmprinter)61 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
62 X86AsmPrinter &asmprinter)
63 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()),
64 MAI(*TM.getMCAsmInfo()), AsmPrinter(asmprinter) {}
65
getMachOMMI() const66 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
67 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
68 }
69
70
71 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
72 /// operand to an MCSymbol.
73 MCSymbol *X86MCInstLower::
GetSymbolFromOperand(const MachineOperand & MO) const74 GetSymbolFromOperand(const MachineOperand &MO) const {
75 const DataLayout *DL = TM.getDataLayout();
76 assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
77
78 SmallString<128> Name;
79 StringRef Suffix;
80
81 switch (MO.getTargetFlags()) {
82 case X86II::MO_DLLIMPORT:
83 // Handle dllimport linkage.
84 Name += "__imp_";
85 break;
86 case X86II::MO_DARWIN_STUB:
87 Suffix = "$stub";
88 break;
89 case X86II::MO_DARWIN_NONLAZY:
90 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
91 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
92 Suffix = "$non_lazy_ptr";
93 break;
94 }
95
96 if (!Suffix.empty())
97 Name += DL->getPrivateGlobalPrefix();
98
99 unsigned PrefixLen = Name.size();
100
101 if (MO.isGlobal()) {
102 const GlobalValue *GV = MO.getGlobal();
103 AsmPrinter.getNameWithPrefix(Name, GV);
104 } else if (MO.isSymbol()) {
105 getMang()->getNameWithPrefix(Name, MO.getSymbolName());
106 } else if (MO.isMBB()) {
107 Name += MO.getMBB()->getSymbol()->getName();
108 }
109 unsigned OrigLen = Name.size() - PrefixLen;
110
111 Name += Suffix;
112 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name);
113
114 StringRef OrigName = StringRef(Name).substr(PrefixLen, OrigLen);
115
116 // If the target flags on the operand changes the name of the symbol, do that
117 // before we return the symbol.
118 switch (MO.getTargetFlags()) {
119 default: break;
120 case X86II::MO_DARWIN_NONLAZY:
121 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
122 MachineModuleInfoImpl::StubValueTy &StubSym =
123 getMachOMMI().getGVStubEntry(Sym);
124 if (!StubSym.getPointer()) {
125 assert(MO.isGlobal() && "Extern symbol not handled yet");
126 StubSym =
127 MachineModuleInfoImpl::
128 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
129 !MO.getGlobal()->hasInternalLinkage());
130 }
131 break;
132 }
133 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
134 MachineModuleInfoImpl::StubValueTy &StubSym =
135 getMachOMMI().getHiddenGVStubEntry(Sym);
136 if (!StubSym.getPointer()) {
137 assert(MO.isGlobal() && "Extern symbol not handled yet");
138 StubSym =
139 MachineModuleInfoImpl::
140 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
141 !MO.getGlobal()->hasInternalLinkage());
142 }
143 break;
144 }
145 case X86II::MO_DARWIN_STUB: {
146 MachineModuleInfoImpl::StubValueTy &StubSym =
147 getMachOMMI().getFnStubEntry(Sym);
148 if (StubSym.getPointer())
149 return Sym;
150
151 if (MO.isGlobal()) {
152 StubSym =
153 MachineModuleInfoImpl::
154 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
155 !MO.getGlobal()->hasInternalLinkage());
156 } else {
157 StubSym =
158 MachineModuleInfoImpl::
159 StubValueTy(Ctx.GetOrCreateSymbol(OrigName), false);
160 }
161 break;
162 }
163 }
164
165 return Sym;
166 }
167
LowerSymbolOperand(const MachineOperand & MO,MCSymbol * Sym) const168 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
169 MCSymbol *Sym) const {
170 // FIXME: We would like an efficient form for this, so we don't have to do a
171 // lot of extra uniquing.
172 const MCExpr *Expr = nullptr;
173 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
174
175 switch (MO.getTargetFlags()) {
176 default: llvm_unreachable("Unknown target flag on GV operand");
177 case X86II::MO_NO_FLAG: // No flag.
178 // These affect the name of the symbol, not any suffix.
179 case X86II::MO_DARWIN_NONLAZY:
180 case X86II::MO_DLLIMPORT:
181 case X86II::MO_DARWIN_STUB:
182 break;
183
184 case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break;
185 case X86II::MO_TLVP_PIC_BASE:
186 Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
187 // Subtract the pic base.
188 Expr = MCBinaryExpr::CreateSub(Expr,
189 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(),
190 Ctx),
191 Ctx);
192 break;
193 case X86II::MO_SECREL: RefKind = MCSymbolRefExpr::VK_SECREL; break;
194 case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break;
195 case X86II::MO_TLSLD: RefKind = MCSymbolRefExpr::VK_TLSLD; break;
196 case X86II::MO_TLSLDM: RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
197 case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
198 case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
199 case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break;
200 case X86II::MO_DTPOFF: RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
201 case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
202 case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
203 case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
204 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break;
205 case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
206 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break;
207 case X86II::MO_PIC_BASE_OFFSET:
208 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
209 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
210 Expr = MCSymbolRefExpr::Create(Sym, Ctx);
211 // Subtract the pic base.
212 Expr = MCBinaryExpr::CreateSub(Expr,
213 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx),
214 Ctx);
215 if (MO.isJTI() && MAI.hasSetDirective()) {
216 // If .set directive is supported, use it to reduce the number of
217 // relocations the assembler will generate for differences between
218 // local labels. This is only safe when the symbols are in the same
219 // section so we are restricting it to jumptable references.
220 MCSymbol *Label = Ctx.CreateTempSymbol();
221 AsmPrinter.OutStreamer.EmitAssignment(Label, Expr);
222 Expr = MCSymbolRefExpr::Create(Label, Ctx);
223 }
224 break;
225 }
226
227 if (!Expr)
228 Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
229
230 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
231 Expr = MCBinaryExpr::CreateAdd(Expr,
232 MCConstantExpr::Create(MO.getOffset(), Ctx),
233 Ctx);
234 return MCOperand::CreateExpr(Expr);
235 }
236
237
238 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
239 /// a short fixed-register form.
SimplifyShortImmForm(MCInst & Inst,unsigned Opcode)240 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
241 unsigned ImmOp = Inst.getNumOperands() - 1;
242 assert(Inst.getOperand(0).isReg() &&
243 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
244 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
245 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
246 Inst.getNumOperands() == 2) && "Unexpected instruction!");
247
248 // Check whether the destination register can be fixed.
249 unsigned Reg = Inst.getOperand(0).getReg();
250 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
251 return;
252
253 // If so, rewrite the instruction.
254 MCOperand Saved = Inst.getOperand(ImmOp);
255 Inst = MCInst();
256 Inst.setOpcode(Opcode);
257 Inst.addOperand(Saved);
258 }
259
260 /// \brief If a movsx instruction has a shorter encoding for the used register
261 /// simplify the instruction to use it instead.
SimplifyMOVSX(MCInst & Inst)262 static void SimplifyMOVSX(MCInst &Inst) {
263 unsigned NewOpcode = 0;
264 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
265 switch (Inst.getOpcode()) {
266 default:
267 llvm_unreachable("Unexpected instruction!");
268 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw
269 if (Op0 == X86::AX && Op1 == X86::AL)
270 NewOpcode = X86::CBW;
271 break;
272 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl
273 if (Op0 == X86::EAX && Op1 == X86::AX)
274 NewOpcode = X86::CWDE;
275 break;
276 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
277 if (Op0 == X86::RAX && Op1 == X86::EAX)
278 NewOpcode = X86::CDQE;
279 break;
280 }
281
282 if (NewOpcode != 0) {
283 Inst = MCInst();
284 Inst.setOpcode(NewOpcode);
285 }
286 }
287
288 /// \brief Simplify things like MOV32rm to MOV32o32a.
SimplifyShortMoveForm(X86AsmPrinter & Printer,MCInst & Inst,unsigned Opcode)289 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
290 unsigned Opcode) {
291 // Don't make these simplifications in 64-bit mode; other assemblers don't
292 // perform them because they make the code larger.
293 if (Printer.getSubtarget().is64Bit())
294 return;
295
296 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
297 unsigned AddrBase = IsStore;
298 unsigned RegOp = IsStore ? 0 : 5;
299 unsigned AddrOp = AddrBase + 3;
300 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
301 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
302 Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
303 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
304 Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
305 (Inst.getOperand(AddrOp).isExpr() ||
306 Inst.getOperand(AddrOp).isImm()) &&
307 "Unexpected instruction!");
308
309 // Check whether the destination register can be fixed.
310 unsigned Reg = Inst.getOperand(RegOp).getReg();
311 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
312 return;
313
314 // Check whether this is an absolute address.
315 // FIXME: We know TLVP symbol refs aren't, but there should be a better way
316 // to do this here.
317 bool Absolute = true;
318 if (Inst.getOperand(AddrOp).isExpr()) {
319 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
320 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
321 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
322 Absolute = false;
323 }
324
325 if (Absolute &&
326 (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
327 Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
328 Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
329 return;
330
331 // If so, rewrite the instruction.
332 MCOperand Saved = Inst.getOperand(AddrOp);
333 MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
334 Inst = MCInst();
335 Inst.setOpcode(Opcode);
336 Inst.addOperand(Saved);
337 Inst.addOperand(Seg);
338 }
339
getRetOpcode(const X86Subtarget & Subtarget)340 static unsigned getRetOpcode(const X86Subtarget &Subtarget)
341 {
342 return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
343 }
344
Lower(const MachineInstr * MI,MCInst & OutMI) const345 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
346 OutMI.setOpcode(MI->getOpcode());
347
348 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
349 const MachineOperand &MO = MI->getOperand(i);
350
351 MCOperand MCOp;
352 switch (MO.getType()) {
353 default:
354 MI->dump();
355 llvm_unreachable("unknown operand type");
356 case MachineOperand::MO_Register:
357 // Ignore all implicit register operands.
358 if (MO.isImplicit()) continue;
359 MCOp = MCOperand::CreateReg(MO.getReg());
360 break;
361 case MachineOperand::MO_Immediate:
362 MCOp = MCOperand::CreateImm(MO.getImm());
363 break;
364 case MachineOperand::MO_MachineBasicBlock:
365 case MachineOperand::MO_GlobalAddress:
366 case MachineOperand::MO_ExternalSymbol:
367 MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
368 break;
369 case MachineOperand::MO_JumpTableIndex:
370 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
371 break;
372 case MachineOperand::MO_ConstantPoolIndex:
373 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
374 break;
375 case MachineOperand::MO_BlockAddress:
376 MCOp = LowerSymbolOperand(MO,
377 AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
378 break;
379 case MachineOperand::MO_RegisterMask:
380 // Ignore call clobbers.
381 continue;
382 }
383
384 OutMI.addOperand(MCOp);
385 }
386
387 // Handle a few special cases to eliminate operand modifiers.
388 ReSimplify:
389 switch (OutMI.getOpcode()) {
390 case X86::LEA64_32r:
391 case X86::LEA64r:
392 case X86::LEA16r:
393 case X86::LEA32r:
394 // LEA should have a segment register, but it must be empty.
395 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
396 "Unexpected # of LEA operands");
397 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
398 "LEA has segment specified!");
399 break;
400
401 case X86::MOV32ri64:
402 OutMI.setOpcode(X86::MOV32ri);
403 break;
404
405 // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
406 // if one of the registers is extended, but other isn't.
407 case X86::VMOVAPDrr:
408 case X86::VMOVAPDYrr:
409 case X86::VMOVAPSrr:
410 case X86::VMOVAPSYrr:
411 case X86::VMOVDQArr:
412 case X86::VMOVDQAYrr:
413 case X86::VMOVDQUrr:
414 case X86::VMOVDQUYrr:
415 case X86::VMOVUPDrr:
416 case X86::VMOVUPDYrr:
417 case X86::VMOVUPSrr:
418 case X86::VMOVUPSYrr: {
419 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
420 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
421 unsigned NewOpc;
422 switch (OutMI.getOpcode()) {
423 default: llvm_unreachable("Invalid opcode");
424 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
425 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
426 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
427 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
428 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
429 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
430 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
431 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
432 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
433 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
434 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
435 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
436 }
437 OutMI.setOpcode(NewOpc);
438 }
439 break;
440 }
441 case X86::VMOVSDrr:
442 case X86::VMOVSSrr: {
443 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
444 X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
445 unsigned NewOpc;
446 switch (OutMI.getOpcode()) {
447 default: llvm_unreachable("Invalid opcode");
448 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
449 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
450 }
451 OutMI.setOpcode(NewOpc);
452 }
453 break;
454 }
455
456 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
457 // inputs modeled as normal uses instead of implicit uses. As such, truncate
458 // off all but the first operand (the callee). FIXME: Change isel.
459 case X86::TAILJMPr64:
460 case X86::CALL64r:
461 case X86::CALL64pcrel32: {
462 unsigned Opcode = OutMI.getOpcode();
463 MCOperand Saved = OutMI.getOperand(0);
464 OutMI = MCInst();
465 OutMI.setOpcode(Opcode);
466 OutMI.addOperand(Saved);
467 break;
468 }
469
470 case X86::EH_RETURN:
471 case X86::EH_RETURN64: {
472 OutMI = MCInst();
473 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
474 break;
475 }
476
477 // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
478 case X86::TAILJMPr:
479 case X86::TAILJMPd:
480 case X86::TAILJMPd64: {
481 unsigned Opcode;
482 switch (OutMI.getOpcode()) {
483 default: llvm_unreachable("Invalid opcode");
484 case X86::TAILJMPr: Opcode = X86::JMP32r; break;
485 case X86::TAILJMPd:
486 case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
487 }
488
489 MCOperand Saved = OutMI.getOperand(0);
490 OutMI = MCInst();
491 OutMI.setOpcode(Opcode);
492 OutMI.addOperand(Saved);
493 break;
494 }
495
496 // These are pseudo-ops for OR to help with the OR->ADD transformation. We do
497 // this with an ugly goto in case the resultant OR uses EAX and needs the
498 // short form.
499 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
500 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
501 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
502 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
503 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
504 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
505 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
506 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
507 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
508
509 // The assembler backend wants to see branches in their small form and relax
510 // them to their large form. The JIT can only handle the large form because
511 // it does not do relaxation. For now, translate the large form to the
512 // small one here.
513 case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
514 case X86::JO_4: OutMI.setOpcode(X86::JO_1); break;
515 case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
516 case X86::JB_4: OutMI.setOpcode(X86::JB_1); break;
517 case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
518 case X86::JE_4: OutMI.setOpcode(X86::JE_1); break;
519 case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
520 case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
521 case X86::JA_4: OutMI.setOpcode(X86::JA_1); break;
522 case X86::JS_4: OutMI.setOpcode(X86::JS_1); break;
523 case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
524 case X86::JP_4: OutMI.setOpcode(X86::JP_1); break;
525 case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
526 case X86::JL_4: OutMI.setOpcode(X86::JL_1); break;
527 case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
528 case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
529 case X86::JG_4: OutMI.setOpcode(X86::JG_1); break;
530
531 // Atomic load and store require a separate pseudo-inst because Acquire
532 // implies mayStore and Release implies mayLoad; fix these to regular MOV
533 // instructions here
534 case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
535 case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
536 case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
537 case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
538 case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
539 case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
540 case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
541 case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
542
543 // We don't currently select the correct instruction form for instructions
544 // which have a short %eax, etc. form. Handle this by custom lowering, for
545 // now.
546 //
547 // Note, we are currently not handling the following instructions:
548 // MOV64ao8, MOV64o8a
549 // XCHG16ar, XCHG32ar, XCHG64ar
550 case X86::MOV8mr_NOREX:
551 case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break;
552 case X86::MOV8rm_NOREX:
553 case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break;
554 case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break;
555 case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break;
556 case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
557 case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
558
559 case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break;
560 case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break;
561 case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break;
562 case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break;
563 case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break;
564 case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break;
565 case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break;
566 case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break;
567 case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break;
568 case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break;
569 case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break;
570 case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break;
571 case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break;
572 case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break;
573 case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break;
574 case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break;
575 case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break;
576 case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break;
577 case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break;
578 case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break;
579 case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break;
580 case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break;
581 case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break;
582 case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break;
583 case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break;
584 case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break;
585 case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break;
586 case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break;
587 case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break;
588 case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
589 case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
590 case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
591 case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break;
592 case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
593 case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
594 case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
595
596 // Try to shrink some forms of movsx.
597 case X86::MOVSX16rr8:
598 case X86::MOVSX32rr16:
599 case X86::MOVSX64rr32:
600 SimplifyMOVSX(OutMI);
601 break;
602 }
603 }
604
LowerTlsAddr(MCStreamer & OutStreamer,X86MCInstLower & MCInstLowering,const MachineInstr & MI,const MCSubtargetInfo & STI)605 static void LowerTlsAddr(MCStreamer &OutStreamer,
606 X86MCInstLower &MCInstLowering,
607 const MachineInstr &MI,
608 const MCSubtargetInfo& STI) {
609
610 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
611 MI.getOpcode() == X86::TLS_base_addr64;
612
613 bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
614
615 MCContext &context = OutStreamer.getContext();
616
617 if (needsPadding)
618 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI);
619
620 MCSymbolRefExpr::VariantKind SRVK;
621 switch (MI.getOpcode()) {
622 case X86::TLS_addr32:
623 case X86::TLS_addr64:
624 SRVK = MCSymbolRefExpr::VK_TLSGD;
625 break;
626 case X86::TLS_base_addr32:
627 SRVK = MCSymbolRefExpr::VK_TLSLDM;
628 break;
629 case X86::TLS_base_addr64:
630 SRVK = MCSymbolRefExpr::VK_TLSLD;
631 break;
632 default:
633 llvm_unreachable("unexpected opcode");
634 }
635
636 MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
637 const MCSymbolRefExpr *symRef = MCSymbolRefExpr::Create(sym, SRVK, context);
638
639 MCInst LEA;
640 if (is64Bits) {
641 LEA.setOpcode(X86::LEA64r);
642 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest
643 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
644 LEA.addOperand(MCOperand::CreateImm(1)); // scale
645 LEA.addOperand(MCOperand::CreateReg(0)); // index
646 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
647 LEA.addOperand(MCOperand::CreateReg(0)); // seg
648 } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
649 LEA.setOpcode(X86::LEA32r);
650 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
651 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base
652 LEA.addOperand(MCOperand::CreateImm(1)); // scale
653 LEA.addOperand(MCOperand::CreateReg(0)); // index
654 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
655 LEA.addOperand(MCOperand::CreateReg(0)); // seg
656 } else {
657 LEA.setOpcode(X86::LEA32r);
658 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
659 LEA.addOperand(MCOperand::CreateReg(0)); // base
660 LEA.addOperand(MCOperand::CreateImm(1)); // scale
661 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index
662 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
663 LEA.addOperand(MCOperand::CreateReg(0)); // seg
664 }
665 OutStreamer.EmitInstruction(LEA, STI);
666
667 if (needsPadding) {
668 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI);
669 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI);
670 OutStreamer.EmitInstruction(MCInstBuilder(X86::REX64_PREFIX), STI);
671 }
672
673 StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
674 MCSymbol *tlsGetAddr = context.GetOrCreateSymbol(name);
675 const MCSymbolRefExpr *tlsRef =
676 MCSymbolRefExpr::Create(tlsGetAddr,
677 MCSymbolRefExpr::VK_PLT,
678 context);
679
680 OutStreamer.EmitInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
681 : X86::CALLpcrel32)
682 .addExpr(tlsRef), STI);
683 }
684
685 /// \brief Emit the optimal amount of multi-byte nops on X86.
EmitNops(MCStreamer & OS,unsigned NumBytes,bool Is64Bit,const MCSubtargetInfo & STI)686 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) {
687 // This works only for 64bit. For 32bit we have to do additional checking if
688 // the CPU supports multi-byte nops.
689 assert(Is64Bit && "EmitNops only supports X86-64");
690 while (NumBytes) {
691 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
692 Opc = IndexReg = Displacement = SegmentReg = 0;
693 BaseReg = X86::RAX; ScaleVal = 1;
694 switch (NumBytes) {
695 case 0: llvm_unreachable("Zero nops?"); break;
696 case 1: NumBytes -= 1; Opc = X86::NOOP; break;
697 case 2: NumBytes -= 2; Opc = X86::XCHG16ar; break;
698 case 3: NumBytes -= 3; Opc = X86::NOOPL; break;
699 case 4: NumBytes -= 4; Opc = X86::NOOPL; Displacement = 8; break;
700 case 5: NumBytes -= 5; Opc = X86::NOOPL; Displacement = 8;
701 IndexReg = X86::RAX; break;
702 case 6: NumBytes -= 6; Opc = X86::NOOPW; Displacement = 8;
703 IndexReg = X86::RAX; break;
704 case 7: NumBytes -= 7; Opc = X86::NOOPL; Displacement = 512; break;
705 case 8: NumBytes -= 8; Opc = X86::NOOPL; Displacement = 512;
706 IndexReg = X86::RAX; break;
707 case 9: NumBytes -= 9; Opc = X86::NOOPW; Displacement = 512;
708 IndexReg = X86::RAX; break;
709 default: NumBytes -= 10; Opc = X86::NOOPW; Displacement = 512;
710 IndexReg = X86::RAX; SegmentReg = X86::CS; break;
711 }
712
713 unsigned NumPrefixes = std::min(NumBytes, 5U);
714 NumBytes -= NumPrefixes;
715 for (unsigned i = 0; i != NumPrefixes; ++i)
716 OS.EmitBytes("\x66");
717
718 switch (Opc) {
719 default: llvm_unreachable("Unexpected opcode"); break;
720 case X86::NOOP:
721 OS.EmitInstruction(MCInstBuilder(Opc), STI);
722 break;
723 case X86::XCHG16ar:
724 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI);
725 break;
726 case X86::NOOPL:
727 case X86::NOOPW:
728 OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg).addImm(ScaleVal)
729 .addReg(IndexReg)
730 .addImm(Displacement)
731 .addReg(SegmentReg), STI);
732 break;
733 }
734 } // while (NumBytes)
735 }
736
737 // Lower a stackmap of the form:
738 // <id>, <shadowBytes>, ...
LowerSTACKMAP(MCStreamer & OS,StackMaps & SM,const MachineInstr & MI,bool Is64Bit,const MCSubtargetInfo & STI)739 static void LowerSTACKMAP(MCStreamer &OS, StackMaps &SM,
740 const MachineInstr &MI, bool Is64Bit, const MCSubtargetInfo& STI) {
741 unsigned NumBytes = MI.getOperand(1).getImm();
742 SM.recordStackMap(MI);
743 // Emit padding.
744 // FIXME: These nops ensure that the stackmap's shadow is covered by
745 // instructions from the same basic block, but the nops should not be
746 // necessary if instructions from the same block follow the stackmap.
747 EmitNops(OS, NumBytes, Is64Bit, STI);
748 }
749
750 // Lower a patchpoint of the form:
751 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
LowerPATCHPOINT(MCStreamer & OS,StackMaps & SM,const MachineInstr & MI,bool Is64Bit,const MCSubtargetInfo & STI)752 static void LowerPATCHPOINT(MCStreamer &OS, StackMaps &SM,
753 const MachineInstr &MI, bool Is64Bit, const MCSubtargetInfo& STI) {
754 assert(Is64Bit && "Patchpoint currently only supports X86-64");
755 SM.recordPatchPoint(MI);
756
757 PatchPointOpers opers(&MI);
758 unsigned ScratchIdx = opers.getNextScratchIdx();
759 unsigned EncodedBytes = 0;
760 int64_t CallTarget = opers.getMetaOper(PatchPointOpers::TargetPos).getImm();
761 if (CallTarget) {
762 // Emit MOV to materialize the target address and the CALL to target.
763 // This is encoded with 12-13 bytes, depending on which register is used.
764 unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
765 if (X86II::isX86_64ExtendedReg(ScratchReg))
766 EncodedBytes = 13;
767 else
768 EncodedBytes = 12;
769 OS.EmitInstruction(MCInstBuilder(X86::MOV64ri).addReg(ScratchReg)
770 .addImm(CallTarget), STI);
771 OS.EmitInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg), STI);
772 }
773 // Emit padding.
774 unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
775 assert(NumBytes >= EncodedBytes &&
776 "Patchpoint can't request size less than the length of a call.");
777
778 EmitNops(OS, NumBytes - EncodedBytes, Is64Bit, STI);
779 }
780
EmitInstruction(const MachineInstr * MI)781 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
782 X86MCInstLower MCInstLowering(*MF, *this);
783 const X86RegisterInfo *RI =
784 static_cast<const X86RegisterInfo *>(TM.getRegisterInfo());
785
786 switch (MI->getOpcode()) {
787 case TargetOpcode::DBG_VALUE:
788 llvm_unreachable("Should be handled target independently");
789
790 // Emit nothing here but a comment if we can.
791 case X86::Int_MemBarrier:
792 OutStreamer.emitRawComment("MEMBARRIER");
793 return;
794
795
796 case X86::EH_RETURN:
797 case X86::EH_RETURN64: {
798 // Lower these as normal, but add some comments.
799 unsigned Reg = MI->getOperand(0).getReg();
800 OutStreamer.AddComment(StringRef("eh_return, addr: %") +
801 X86ATTInstPrinter::getRegisterName(Reg));
802 break;
803 }
804 case X86::TAILJMPr:
805 case X86::TAILJMPd:
806 case X86::TAILJMPd64:
807 // Lower these as normal, but add some comments.
808 OutStreamer.AddComment("TAILCALL");
809 break;
810
811 case X86::TLS_addr32:
812 case X86::TLS_addr64:
813 case X86::TLS_base_addr32:
814 case X86::TLS_base_addr64:
815 return LowerTlsAddr(OutStreamer, MCInstLowering, *MI, getSubtargetInfo());
816
817 case X86::MOVPC32r: {
818 // This is a pseudo op for a two instruction sequence with a label, which
819 // looks like:
820 // call "L1$pb"
821 // "L1$pb":
822 // popl %esi
823
824 // Emit the call.
825 MCSymbol *PICBase = MF->getPICBaseSymbol();
826 // FIXME: We would like an efficient form for this, so we don't have to do a
827 // lot of extra uniquing.
828 EmitToStreamer(OutStreamer, MCInstBuilder(X86::CALLpcrel32)
829 .addExpr(MCSymbolRefExpr::Create(PICBase, OutContext)));
830
831 // Emit the label.
832 OutStreamer.EmitLabel(PICBase);
833
834 // popl $reg
835 EmitToStreamer(OutStreamer, MCInstBuilder(X86::POP32r)
836 .addReg(MI->getOperand(0).getReg()));
837 return;
838 }
839
840 case X86::ADD32ri: {
841 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
842 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
843 break;
844
845 // Okay, we have something like:
846 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
847
848 // For this, we want to print something like:
849 // MYGLOBAL + (. - PICBASE)
850 // However, we can't generate a ".", so just emit a new label here and refer
851 // to it.
852 MCSymbol *DotSym = OutContext.CreateTempSymbol();
853 OutStreamer.EmitLabel(DotSym);
854
855 // Now that we have emitted the label, lower the complex operand expression.
856 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
857
858 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
859 const MCExpr *PICBase =
860 MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext);
861 DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
862
863 DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
864 DotExpr, OutContext);
865
866 EmitToStreamer(OutStreamer, MCInstBuilder(X86::ADD32ri)
867 .addReg(MI->getOperand(0).getReg())
868 .addReg(MI->getOperand(1).getReg())
869 .addExpr(DotExpr));
870 return;
871 }
872
873 case TargetOpcode::STACKMAP:
874 return LowerSTACKMAP(OutStreamer, SM, *MI, Subtarget->is64Bit(), getSubtargetInfo());
875
876 case TargetOpcode::PATCHPOINT:
877 return LowerPATCHPOINT(OutStreamer, SM, *MI, Subtarget->is64Bit(), getSubtargetInfo());
878
879 case X86::MORESTACK_RET:
880 EmitToStreamer(OutStreamer, MCInstBuilder(getRetOpcode(*Subtarget)));
881 return;
882
883 case X86::MORESTACK_RET_RESTORE_R10:
884 // Return, then restore R10.
885 EmitToStreamer(OutStreamer, MCInstBuilder(getRetOpcode(*Subtarget)));
886 EmitToStreamer(OutStreamer, MCInstBuilder(X86::MOV64rr)
887 .addReg(X86::R10)
888 .addReg(X86::RAX));
889 return;
890
891 case X86::SEH_PushReg:
892 OutStreamer.EmitWinCFIPushReg(RI->getSEHRegNum(MI->getOperand(0).getImm()));
893 return;
894
895 case X86::SEH_SaveReg:
896 OutStreamer.EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()),
897 MI->getOperand(1).getImm());
898 return;
899
900 case X86::SEH_SaveXMM:
901 OutStreamer.EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()),
902 MI->getOperand(1).getImm());
903 return;
904
905 case X86::SEH_StackAlloc:
906 OutStreamer.EmitWinCFIAllocStack(MI->getOperand(0).getImm());
907 return;
908
909 case X86::SEH_SetFrame:
910 OutStreamer.EmitWinCFISetFrame(RI->getSEHRegNum(MI->getOperand(0).getImm()),
911 MI->getOperand(1).getImm());
912 return;
913
914 case X86::SEH_PushFrame:
915 OutStreamer.EmitWinCFIPushFrame(MI->getOperand(0).getImm());
916 return;
917
918 case X86::SEH_EndPrologue:
919 OutStreamer.EmitWinCFIEndProlog();
920 return;
921 }
922
923 MCInst TmpInst;
924 MCInstLowering.Lower(MI, TmpInst);
925 EmitToStreamer(OutStreamer, TmpInst);
926 }
927