1 //===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares codegen opcodes and related utilities. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_ISDOPCODES_H 15 #define LLVM_CODEGEN_ISDOPCODES_H 16 17 namespace llvm { 18 19 /// ISD namespace - This namespace contains an enum which represents all of the 20 /// SelectionDAG node types and value types. 21 /// 22 namespace ISD { 23 24 //===--------------------------------------------------------------------===// 25 /// ISD::NodeType enum - This enum defines the target-independent operators 26 /// for a SelectionDAG. 27 /// 28 /// Targets may also define target-dependent operator codes for SDNodes. For 29 /// example, on x86, these are the enum values in the X86ISD namespace. 30 /// Targets should aim to use target-independent operators to model their 31 /// instruction sets as much as possible, and only use target-dependent 32 /// operators when they have special requirements. 33 /// 34 /// Finally, during and after selection proper, SNodes may use special 35 /// operator codes that correspond directly with MachineInstr opcodes. These 36 /// are used to represent selected instructions. See the isMachineOpcode() 37 /// and getMachineOpcode() member functions of SDNode. 38 /// 39 enum NodeType { 40 /// DELETED_NODE - This is an illegal value that is used to catch 41 /// errors. This opcode is not a legal opcode for any node. 42 DELETED_NODE, 43 44 /// EntryToken - This is the marker used to indicate the start of a region. 45 EntryToken, 46 47 /// TokenFactor - This node takes multiple tokens as input and produces a 48 /// single token result. This is used to represent the fact that the operand 49 /// operators are independent of each other. 50 TokenFactor, 51 52 /// AssertSext, AssertZext - These nodes record if a register contains a 53 /// value that has already been zero or sign extended from a narrower type. 54 /// These nodes take two operands. The first is the node that has already 55 /// been extended, and the second is a value type node indicating the width 56 /// of the extension 57 AssertSext, AssertZext, 58 59 /// Various leaf nodes. 60 BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask, 61 Constant, ConstantFP, 62 GlobalAddress, GlobalTLSAddress, FrameIndex, 63 JumpTable, ConstantPool, ExternalSymbol, BlockAddress, 64 65 /// The address of the GOT 66 GLOBAL_OFFSET_TABLE, 67 68 /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and 69 /// llvm.returnaddress on the DAG. These nodes take one operand, the index 70 /// of the frame or return address to return. An index of zero corresponds 71 /// to the current function's frame or return address, an index of one to 72 /// the parent's frame or return address, and so on. 73 FRAMEADDR, RETURNADDR, 74 75 /// READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on 76 /// the DAG, which implements the named register global variables extension. 77 READ_REGISTER, 78 WRITE_REGISTER, 79 80 /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to 81 /// first (possible) on-stack argument. This is needed for correct stack 82 /// adjustment during unwind. 83 FRAME_TO_ARGS_OFFSET, 84 85 /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 86 /// 'eh_return' gcc dwarf builtin, which is used to return from 87 /// exception. The general meaning is: adjust stack by OFFSET and pass 88 /// execution to HANDLER. Many platform-related details also :) 89 EH_RETURN, 90 91 /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) 92 /// This corresponds to the eh.sjlj.setjmp intrinsic. 93 /// It takes an input chain and a pointer to the jump buffer as inputs 94 /// and returns an outchain. 95 EH_SJLJ_SETJMP, 96 97 /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) 98 /// This corresponds to the eh.sjlj.longjmp intrinsic. 99 /// It takes an input chain and a pointer to the jump buffer as inputs 100 /// and returns an outchain. 101 EH_SJLJ_LONGJMP, 102 103 /// TargetConstant* - Like Constant*, but the DAG does not do any folding, 104 /// simplification, or lowering of the constant. They are used for constants 105 /// which are known to fit in the immediate fields of their users, or for 106 /// carrying magic numbers which are not values which need to be 107 /// materialized in registers. 108 TargetConstant, 109 TargetConstantFP, 110 111 /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or 112 /// anything else with this node, and this is valid in the target-specific 113 /// dag, turning into a GlobalAddress operand. 114 TargetGlobalAddress, 115 TargetGlobalTLSAddress, 116 TargetFrameIndex, 117 TargetJumpTable, 118 TargetConstantPool, 119 TargetExternalSymbol, 120 TargetBlockAddress, 121 122 /// TargetIndex - Like a constant pool entry, but with completely 123 /// target-dependent semantics. Holds target flags, a 32-bit index, and a 124 /// 64-bit index. Targets can use this however they like. 125 TargetIndex, 126 127 /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) 128 /// This node represents a target intrinsic function with no side effects. 129 /// The first operand is the ID number of the intrinsic from the 130 /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The 131 /// node returns the result of the intrinsic. 132 INTRINSIC_WO_CHAIN, 133 134 /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) 135 /// This node represents a target intrinsic function with side effects that 136 /// returns a result. The first operand is a chain pointer. The second is 137 /// the ID number of the intrinsic from the llvm::Intrinsic namespace. The 138 /// operands to the intrinsic follow. The node has two results, the result 139 /// of the intrinsic and an output chain. 140 INTRINSIC_W_CHAIN, 141 142 /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) 143 /// This node represents a target intrinsic function with side effects that 144 /// does not return a result. The first operand is a chain pointer. The 145 /// second is the ID number of the intrinsic from the llvm::Intrinsic 146 /// namespace. The operands to the intrinsic follow. 147 INTRINSIC_VOID, 148 149 /// CopyToReg - This node has three operands: a chain, a register number to 150 /// set to this value, and a value. 151 CopyToReg, 152 153 /// CopyFromReg - This node indicates that the input value is a virtual or 154 /// physical register that is defined outside of the scope of this 155 /// SelectionDAG. The register is available from the RegisterSDNode object. 156 CopyFromReg, 157 158 /// UNDEF - An undefined node. 159 UNDEF, 160 161 /// EXTRACT_ELEMENT - This is used to get the lower or upper (determined by 162 /// a Constant, which is required to be operand #1) half of the integer or 163 /// float value specified as operand #0. This is only for use before 164 /// legalization, for values that will be broken into multiple registers. 165 EXTRACT_ELEMENT, 166 167 /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways. 168 /// Given two values of the same integer value type, this produces a value 169 /// twice as big. Like EXTRACT_ELEMENT, this can only be used before 170 /// legalization. 171 BUILD_PAIR, 172 173 /// MERGE_VALUES - This node takes multiple discrete operands and returns 174 /// them all as its individual results. This nodes has exactly the same 175 /// number of inputs and outputs. This node is useful for some pieces of the 176 /// code generator that want to think about a single node with multiple 177 /// results, not multiple nodes. 178 MERGE_VALUES, 179 180 /// Simple integer binary arithmetic operators. 181 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, 182 183 /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing 184 /// a signed/unsigned value of type i[2*N], and return the full value as 185 /// two results, each of type iN. 186 SMUL_LOHI, UMUL_LOHI, 187 188 /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and 189 /// remainder result. 190 SDIVREM, UDIVREM, 191 192 /// CARRY_FALSE - This node is used when folding other nodes, 193 /// like ADDC/SUBC, which indicate the carry result is always false. 194 CARRY_FALSE, 195 196 /// Carry-setting nodes for multiple precision addition and subtraction. 197 /// These nodes take two operands of the same value type, and produce two 198 /// results. The first result is the normal add or sub result, the second 199 /// result is the carry flag result. 200 ADDC, SUBC, 201 202 /// Carry-using nodes for multiple precision addition and subtraction. These 203 /// nodes take three operands: The first two are the normal lhs and rhs to 204 /// the add or sub, and the third is the input carry flag. These nodes 205 /// produce two results; the normal result of the add or sub, and the output 206 /// carry flag. These nodes both read and write a carry flag to allow them 207 /// to them to be chained together for add and sub of arbitrarily large 208 /// values. 209 ADDE, SUBE, 210 211 /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition. 212 /// These nodes take two operands: the normal LHS and RHS to the add. They 213 /// produce two results: the normal result of the add, and a boolean that 214 /// indicates if an overflow occurred (*not* a flag, because it may be store 215 /// to memory, etc.). If the type of the boolean is not i1 then the high 216 /// bits conform to getBooleanContents. 217 /// These nodes are generated from llvm.[su]add.with.overflow intrinsics. 218 SADDO, UADDO, 219 220 /// Same for subtraction. 221 SSUBO, USUBO, 222 223 /// Same for multiplication. 224 SMULO, UMULO, 225 226 /// Simple binary floating point operators. 227 FADD, FSUB, FMUL, FMA, FDIV, FREM, 228 229 /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This 230 /// DAG node does not require that X and Y have the same type, just that the 231 /// are both floating point. X and the result must have the same type. 232 /// FCOPYSIGN(f32, f64) is allowed. 233 FCOPYSIGN, 234 235 /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point 236 /// value as an integer 0/1 value. 237 FGETSIGN, 238 239 /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the 240 /// specified, possibly variable, elements. The number of elements is 241 /// required to be a power of two. The types of the operands must all be 242 /// the same and must match the vector element type, except that integer 243 /// types are allowed to be larger than the element type, in which case 244 /// the operands are implicitly truncated. 245 BUILD_VECTOR, 246 247 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element 248 /// at IDX replaced with VAL. If the type of VAL is larger than the vector 249 /// element type then VAL is truncated before replacement. 250 INSERT_VECTOR_ELT, 251 252 /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR 253 /// identified by the (potentially variable) element number IDX. If the 254 /// return type is an integer type larger than the element type of the 255 /// vector, the result is extended to the width of the return type. 256 EXTRACT_VECTOR_ELT, 257 258 /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of 259 /// vector type with the same length and element type, this produces a 260 /// concatenated vector result value, with length equal to the sum of the 261 /// lengths of the input vectors. 262 CONCAT_VECTORS, 263 264 /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector 265 /// with VECTOR2 inserted into VECTOR1 at the (potentially 266 /// variable) element number IDX, which must be a multiple of the 267 /// VECTOR2 vector length. The elements of VECTOR1 starting at 268 /// IDX are overwritten with VECTOR2. Elements IDX through 269 /// vector_length(VECTOR2) must be valid VECTOR1 indices. 270 INSERT_SUBVECTOR, 271 272 /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an 273 /// vector value) starting with the element number IDX, which must be a 274 /// constant multiple of the result vector length. 275 EXTRACT_SUBVECTOR, 276 277 /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as 278 /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int 279 /// values that indicate which value (or undef) each result element will 280 /// get. These constant ints are accessible through the 281 /// ShuffleVectorSDNode class. This is quite similar to the Altivec 282 /// 'vperm' instruction, except that the indices must be constants and are 283 /// in terms of the element size of VEC1/VEC2, not in terms of bytes. 284 VECTOR_SHUFFLE, 285 286 /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a 287 /// scalar value into element 0 of the resultant vector type. The top 288 /// elements 1 to N-1 of the N-element vector are undefined. The type 289 /// of the operand must match the vector element type, except when they 290 /// are integer types. In this case the operand is allowed to be wider 291 /// than the vector element type, and is implicitly truncated to it. 292 SCALAR_TO_VECTOR, 293 294 /// MULHU/MULHS - Multiply high - Multiply two integers of type iN, 295 /// producing an unsigned/signed value of type i[2*N], then return the top 296 /// part. 297 MULHU, MULHS, 298 299 /// Bitwise operators - logical and, logical or, logical xor. 300 AND, OR, XOR, 301 302 /// Shift and rotation operations. After legalization, the type of the 303 /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization 304 /// the shift amount can be any type, but care must be taken to ensure it is 305 /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but before 306 /// legalization, types like i1024 can occur and i8 doesn't have enough bits 307 /// to represent the shift amount. 308 /// When the 1st operand is a vector, the shift amount must be in the same 309 /// type. (TLI.getShiftAmountTy() will return the same type when the input 310 /// type is a vector.) 311 SHL, SRA, SRL, ROTL, ROTR, 312 313 /// Byte Swap and Counting operators. 314 BSWAP, CTTZ, CTLZ, CTPOP, 315 316 /// Bit counting operators with an undefined result for zero inputs. 317 CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF, 318 319 /// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not 320 /// i1 then the high bits must conform to getBooleanContents. 321 SELECT, 322 323 /// Select with a vector condition (op #0) and two vector operands (ops #1 324 /// and #2), returning a vector result. All vectors have the same length. 325 /// Much like the scalar select and setcc, each bit in the condition selects 326 /// whether the corresponding result element is taken from op #1 or op #2. 327 /// At first, the VSELECT condition is of vXi1 type. Later, targets may 328 /// change the condition type in order to match the VSELECT node using a 329 /// pattern. The condition follows the BooleanContent format of the target. 330 VSELECT, 331 332 /// Select with condition operator - This selects between a true value and 333 /// a false value (ops #2 and #3) based on the boolean result of comparing 334 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the 335 /// condition code in op #4, a CondCodeSDNode. 336 SELECT_CC, 337 338 /// SetCC operator - This evaluates to a true value iff the condition is 339 /// true. If the result value type is not i1 then the high bits conform 340 /// to getBooleanContents. The operands to this are the left and right 341 /// operands to compare (ops #0, and #1) and the condition code to compare 342 /// them with (op #2) as a CondCodeSDNode. If the operands are vector types 343 /// then the result type must also be a vector type. 344 SETCC, 345 346 /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded 347 /// integer shift operations, just like ADD/SUB_PARTS. The operation 348 /// ordering is: 349 /// [Lo,Hi] = op [LoLHS,HiLHS], Amt 350 SHL_PARTS, SRA_PARTS, SRL_PARTS, 351 352 /// Conversion operators. These are all single input single output 353 /// operations. For all of these, the result type must be strictly 354 /// wider or narrower (depending on the operation) than the source 355 /// type. 356 357 /// SIGN_EXTEND - Used for integer types, replicating the sign bit 358 /// into new bits. 359 SIGN_EXTEND, 360 361 /// ZERO_EXTEND - Used for integer types, zeroing the new bits. 362 ZERO_EXTEND, 363 364 /// ANY_EXTEND - Used for integer types. The high bits are undefined. 365 ANY_EXTEND, 366 367 /// TRUNCATE - Completely drop the high bits. 368 TRUNCATE, 369 370 /// [SU]INT_TO_FP - These operators convert integers (whose interpreted sign 371 /// depends on the first letter) to floating point. 372 SINT_TO_FP, 373 UINT_TO_FP, 374 375 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to 376 /// sign extend a small value in a large integer register (e.g. sign 377 /// extending the low 8 bits of a 32-bit register to fill the top 24 bits 378 /// with the 7th bit). The size of the smaller type is indicated by the 1th 379 /// operand, a ValueType node. 380 SIGN_EXTEND_INREG, 381 382 /// ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an 383 /// in-register any-extension of the low lanes of an integer vector. The 384 /// result type must have fewer elements than the operand type, and those 385 /// elements must be larger integer types such that the total size of the 386 /// operand type and the result type match. Each of the low operand 387 /// elements is any-extended into the corresponding, wider result 388 /// elements with the high bits becoming undef. 389 ANY_EXTEND_VECTOR_INREG, 390 391 /// SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an 392 /// in-register sign-extension of the low lanes of an integer vector. The 393 /// result type must have fewer elements than the operand type, and those 394 /// elements must be larger integer types such that the total size of the 395 /// operand type and the result type match. Each of the low operand 396 /// elements is sign-extended into the corresponding, wider result 397 /// elements. 398 // FIXME: The SIGN_EXTEND_INREG node isn't specifically limited to 399 // scalars, but it also doesn't handle vectors well. Either it should be 400 // restricted to scalars or this node (and its handling) should be merged 401 // into it. 402 SIGN_EXTEND_VECTOR_INREG, 403 404 /// ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an 405 /// in-register zero-extension of the low lanes of an integer vector. The 406 /// result type must have fewer elements than the operand type, and those 407 /// elements must be larger integer types such that the total size of the 408 /// operand type and the result type match. Each of the low operand 409 /// elements is zero-extended into the corresponding, wider result 410 /// elements. 411 ZERO_EXTEND_VECTOR_INREG, 412 413 /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned 414 /// integer. 415 FP_TO_SINT, 416 FP_TO_UINT, 417 418 /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type 419 /// down to the precision of the destination VT. TRUNC is a flag, which is 420 /// always an integer that is zero or one. If TRUNC is 0, this is a 421 /// normal rounding, if it is 1, this FP_ROUND is known to not change the 422 /// value of Y. 423 /// 424 /// The TRUNC = 1 case is used in cases where we know that the value will 425 /// not be modified by the node, because Y is not using any of the extra 426 /// precision of source type. This allows certain transformations like 427 /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for 428 /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed. 429 FP_ROUND, 430 431 /// FLT_ROUNDS_ - Returns current rounding mode: 432 /// -1 Undefined 433 /// 0 Round to 0 434 /// 1 Round to nearest 435 /// 2 Round to +inf 436 /// 3 Round to -inf 437 FLT_ROUNDS_, 438 439 /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and 440 /// rounds it to a floating point value. It then promotes it and returns it 441 /// in a register of the same size. This operation effectively just 442 /// discards excess precision. The type to round down to is specified by 443 /// the VT operand, a VTSDNode. 444 FP_ROUND_INREG, 445 446 /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type. 447 FP_EXTEND, 448 449 /// BITCAST - This operator converts between integer, vector and FP 450 /// values, as if the value was stored to memory with one type and loaded 451 /// from the same address with the other type (or equivalently for vector 452 /// format conversions, etc). The source and result are required to have 453 /// the same bit size (e.g. f32 <-> i32). This can also be used for 454 /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by 455 /// getNode(). 456 BITCAST, 457 458 /// ADDRSPACECAST - This operator converts between pointers of different 459 /// address spaces. 460 ADDRSPACECAST, 461 462 /// CONVERT_RNDSAT - This operator is used to support various conversions 463 /// between various types (float, signed, unsigned and vectors of those 464 /// types) with rounding and saturation. NOTE: Avoid using this operator as 465 /// most target don't support it and the operator might be removed in the 466 /// future. It takes the following arguments: 467 /// 0) value 468 /// 1) dest type (type to convert to) 469 /// 2) src type (type to convert from) 470 /// 3) rounding imm 471 /// 4) saturation imm 472 /// 5) ISD::CvtCode indicating the type of conversion to do 473 CONVERT_RNDSAT, 474 475 /// FP16_TO_FP32, FP32_TO_FP16 - These operators are used to perform 476 /// promotions and truncation for half-precision (16 bit) floating 477 /// numbers. We need special nodes since FP16 is a storage-only type with 478 /// special semantics of operations. 479 FP16_TO_FP32, FP32_TO_FP16, 480 481 /// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, 482 /// FLOG, FLOG2, FLOG10, FEXP, FEXP2, 483 /// FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary 484 /// floating point operations. These are inspired by libm. 485 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, 486 FLOG, FLOG2, FLOG10, FEXP, FEXP2, 487 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR, 488 489 /// FSINCOS - Compute both fsin and fcos as a single operation. 490 FSINCOS, 491 492 /// LOAD and STORE have token chains as their first operand, then the same 493 /// operands as an LLVM load/store instruction, then an offset node that 494 /// is added / subtracted from the base pointer to form the address (for 495 /// indexed memory ops). 496 LOAD, STORE, 497 498 /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned 499 /// to a specified boundary. This node always has two return values: a new 500 /// stack pointer value and a chain. The first operand is the token chain, 501 /// the second is the number of bytes to allocate, and the third is the 502 /// alignment boundary. The size is guaranteed to be a multiple of the 503 /// stack alignment, and the alignment is guaranteed to be bigger than the 504 /// stack alignment (if required) or 0 to get standard stack alignment. 505 DYNAMIC_STACKALLOC, 506 507 /// Control flow instructions. These all have token chains. 508 509 /// BR - Unconditional branch. The first operand is the chain 510 /// operand, the second is the MBB to branch to. 511 BR, 512 513 /// BRIND - Indirect branch. The first operand is the chain, the second 514 /// is the value to branch to, which must be of the same type as the 515 /// target's pointer type. 516 BRIND, 517 518 /// BR_JT - Jumptable branch. The first operand is the chain, the second 519 /// is the jumptable index, the last one is the jumptable entry index. 520 BR_JT, 521 522 /// BRCOND - Conditional branch. The first operand is the chain, the 523 /// second is the condition, the third is the block to branch to if the 524 /// condition is true. If the type of the condition is not i1, then the 525 /// high bits must conform to getBooleanContents. 526 BRCOND, 527 528 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in 529 /// that the condition is represented as condition code, and two nodes to 530 /// compare, rather than as a combined SetCC node. The operands in order 531 /// are chain, cc, lhs, rhs, block to branch to if condition is true. 532 BR_CC, 533 534 /// INLINEASM - Represents an inline asm block. This node always has two 535 /// return values: a chain and a flag result. The inputs are as follows: 536 /// Operand #0 : Input chain. 537 /// Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string. 538 /// Operand #2 : a MDNodeSDNode with the !srcloc metadata. 539 /// Operand #3 : HasSideEffect, IsAlignStack bits. 540 /// After this, it is followed by a list of operands with this format: 541 /// ConstantSDNode: Flags that encode whether it is a mem or not, the 542 /// of operands that follow, etc. See InlineAsm.h. 543 /// ... however many operands ... 544 /// Operand #last: Optional, an incoming flag. 545 /// 546 /// The variable width operands are required to represent target addressing 547 /// modes as a single "operand", even though they may have multiple 548 /// SDOperands. 549 INLINEASM, 550 551 /// EH_LABEL - Represents a label in mid basic block used to track 552 /// locations needed for debug and exception handling tables. These nodes 553 /// take a chain as input and return a chain. 554 EH_LABEL, 555 556 /// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a 557 /// value, the same type as the pointer type for the system, and an output 558 /// chain. 559 STACKSAVE, 560 561 /// STACKRESTORE has two operands, an input chain and a pointer to restore 562 /// to it returns an output chain. 563 STACKRESTORE, 564 565 /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end 566 /// of a call sequence, and carry arbitrary information that target might 567 /// want to know. The first operand is a chain, the rest are specified by 568 /// the target and not touched by the DAG optimizers. 569 /// CALLSEQ_START..CALLSEQ_END pairs may not be nested. 570 CALLSEQ_START, // Beginning of a call sequence 571 CALLSEQ_END, // End of a call sequence 572 573 /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, 574 /// and the alignment. It returns a pair of values: the vaarg value and a 575 /// new chain. 576 VAARG, 577 578 /// VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, 579 /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the 580 /// source. 581 VACOPY, 582 583 /// VAEND, VASTART - VAEND and VASTART have three operands: an input chain, 584 /// pointer, and a SRCVALUE. 585 VAEND, VASTART, 586 587 /// SRCVALUE - This is a node type that holds a Value* that is used to 588 /// make reference to a value in the LLVM IR. 589 SRCVALUE, 590 591 /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to 592 /// reference metadata in the IR. 593 MDNODE_SDNODE, 594 595 /// PCMARKER - This corresponds to the pcmarker intrinsic. 596 PCMARKER, 597 598 /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic. 599 /// The only operand is a chain and a value and a chain are produced. The 600 /// value is the contents of the architecture specific cycle counter like 601 /// register (or other high accuracy low latency clock source) 602 READCYCLECOUNTER, 603 604 /// HANDLENODE node - Used as a handle for various purposes. 605 HANDLENODE, 606 607 /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. It 608 /// takes as input a token chain, the pointer to the trampoline, the pointer 609 /// to the nested function, the pointer to pass for the 'nest' parameter, a 610 /// SRCVALUE for the trampoline and another for the nested function 611 /// (allowing targets to access the original Function*). 612 /// It produces a token chain as output. 613 INIT_TRAMPOLINE, 614 615 /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic. 616 /// It takes a pointer to the trampoline and produces a (possibly) new 617 /// pointer to the same trampoline with platform-specific adjustments 618 /// applied. The pointer it returns points to an executable block of code. 619 ADJUST_TRAMPOLINE, 620 621 /// TRAP - Trapping instruction 622 TRAP, 623 624 /// DEBUGTRAP - Trap intended to get the attention of a debugger. 625 DEBUGTRAP, 626 627 /// PREFETCH - This corresponds to a prefetch intrinsic. The first operand 628 /// is the chain. The other operands are the address to prefetch, 629 /// read / write specifier, locality specifier and instruction / data cache 630 /// specifier. 631 PREFETCH, 632 633 /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) 634 /// This corresponds to the fence instruction. It takes an input chain, and 635 /// two integer constants: an AtomicOrdering and a SynchronizationScope. 636 ATOMIC_FENCE, 637 638 /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) 639 /// This corresponds to "load atomic" instruction. 640 ATOMIC_LOAD, 641 642 /// OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) 643 /// This corresponds to "store atomic" instruction. 644 ATOMIC_STORE, 645 646 /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) 647 /// For double-word atomic operations: 648 /// ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmpLo, cmpHi, 649 /// swapLo, swapHi) 650 /// This corresponds to the cmpxchg instruction. 651 ATOMIC_CMP_SWAP, 652 653 /// Val, Success, OUTCHAIN 654 /// = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) 655 /// N.b. this is still a strong cmpxchg operation, so 656 /// Success == "Val == cmp". 657 ATOMIC_CMP_SWAP_WITH_SUCCESS, 658 659 /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) 660 /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) 661 /// For double-word atomic operations: 662 /// ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) 663 /// ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) 664 /// These correspond to the atomicrmw instruction. 665 ATOMIC_SWAP, 666 ATOMIC_LOAD_ADD, 667 ATOMIC_LOAD_SUB, 668 ATOMIC_LOAD_AND, 669 ATOMIC_LOAD_OR, 670 ATOMIC_LOAD_XOR, 671 ATOMIC_LOAD_NAND, 672 ATOMIC_LOAD_MIN, 673 ATOMIC_LOAD_MAX, 674 ATOMIC_LOAD_UMIN, 675 ATOMIC_LOAD_UMAX, 676 677 /// This corresponds to the llvm.lifetime.* intrinsics. The first operand 678 /// is the chain and the second operand is the alloca pointer. 679 LIFETIME_START, LIFETIME_END, 680 681 /// BUILTIN_OP_END - This must be the last enum value in this list. 682 /// The target-specific pre-isel opcode values start here. 683 BUILTIN_OP_END 684 }; 685 686 /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations 687 /// which do not reference a specific memory location should be less than 688 /// this value. Those that do must not be less than this value, and can 689 /// be used with SelectionDAG::getMemIntrinsicNode. 690 static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+180; 691 692 //===--------------------------------------------------------------------===// 693 /// MemIndexedMode enum - This enum defines the load / store indexed 694 /// addressing modes. 695 /// 696 /// UNINDEXED "Normal" load / store. The effective address is already 697 /// computed and is available in the base pointer. The offset 698 /// operand is always undefined. In addition to producing a 699 /// chain, an unindexed load produces one value (result of the 700 /// load); an unindexed store does not produce a value. 701 /// 702 /// PRE_INC Similar to the unindexed mode where the effective address is 703 /// PRE_DEC the value of the base pointer add / subtract the offset. 704 /// It considers the computation as being folded into the load / 705 /// store operation (i.e. the load / store does the address 706 /// computation as well as performing the memory transaction). 707 /// The base operand is always undefined. In addition to 708 /// producing a chain, pre-indexed load produces two values 709 /// (result of the load and the result of the address 710 /// computation); a pre-indexed store produces one value (result 711 /// of the address computation). 712 /// 713 /// POST_INC The effective address is the value of the base pointer. The 714 /// POST_DEC value of the offset operand is then added to / subtracted 715 /// from the base after memory transaction. In addition to 716 /// producing a chain, post-indexed load produces two values 717 /// (the result of the load and the result of the base +/- offset 718 /// computation); a post-indexed store produces one value (the 719 /// the result of the base +/- offset computation). 720 enum MemIndexedMode { 721 UNINDEXED = 0, 722 PRE_INC, 723 PRE_DEC, 724 POST_INC, 725 POST_DEC, 726 LAST_INDEXED_MODE 727 }; 728 729 //===--------------------------------------------------------------------===// 730 /// LoadExtType enum - This enum defines the three variants of LOADEXT 731 /// (load with extension). 732 /// 733 /// SEXTLOAD loads the integer operand and sign extends it to a larger 734 /// integer result type. 735 /// ZEXTLOAD loads the integer operand and zero extends it to a larger 736 /// integer result type. 737 /// EXTLOAD is used for two things: floating point extending loads and 738 /// integer extending loads [the top bits are undefined]. 739 enum LoadExtType { 740 NON_EXTLOAD = 0, 741 EXTLOAD, 742 SEXTLOAD, 743 ZEXTLOAD, 744 LAST_LOADEXT_TYPE 745 }; 746 747 NodeType getExtForLoadExtType(LoadExtType); 748 749 //===--------------------------------------------------------------------===// 750 /// ISD::CondCode enum - These are ordered carefully to make the bitfields 751 /// below work out, when considering SETFALSE (something that never exists 752 /// dynamically) as 0. "U" -> Unsigned (for integer operands) or Unordered 753 /// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal 754 /// to. If the "N" column is 1, the result of the comparison is undefined if 755 /// the input is a NAN. 756 /// 757 /// All of these (except for the 'always folded ops') should be handled for 758 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT, 759 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used. 760 /// 761 /// Note that these are laid out in a specific order to allow bit-twiddling 762 /// to transform conditions. 763 enum CondCode { 764 // Opcode N U L G E Intuitive operation 765 SETFALSE, // 0 0 0 0 Always false (always folded) 766 SETOEQ, // 0 0 0 1 True if ordered and equal 767 SETOGT, // 0 0 1 0 True if ordered and greater than 768 SETOGE, // 0 0 1 1 True if ordered and greater than or equal 769 SETOLT, // 0 1 0 0 True if ordered and less than 770 SETOLE, // 0 1 0 1 True if ordered and less than or equal 771 SETONE, // 0 1 1 0 True if ordered and operands are unequal 772 SETO, // 0 1 1 1 True if ordered (no nans) 773 SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y) 774 SETUEQ, // 1 0 0 1 True if unordered or equal 775 SETUGT, // 1 0 1 0 True if unordered or greater than 776 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal 777 SETULT, // 1 1 0 0 True if unordered or less than 778 SETULE, // 1 1 0 1 True if unordered, less than, or equal 779 SETUNE, // 1 1 1 0 True if unordered or not equal 780 SETTRUE, // 1 1 1 1 Always true (always folded) 781 // Don't care operations: undefined if the input is a nan. 782 SETFALSE2, // 1 X 0 0 0 Always false (always folded) 783 SETEQ, // 1 X 0 0 1 True if equal 784 SETGT, // 1 X 0 1 0 True if greater than 785 SETGE, // 1 X 0 1 1 True if greater than or equal 786 SETLT, // 1 X 1 0 0 True if less than 787 SETLE, // 1 X 1 0 1 True if less than or equal 788 SETNE, // 1 X 1 1 0 True if not equal 789 SETTRUE2, // 1 X 1 1 1 Always true (always folded) 790 791 SETCC_INVALID // Marker value. 792 }; 793 794 /// isSignedIntSetCC - Return true if this is a setcc instruction that 795 /// performs a signed comparison when used with integer operands. isSignedIntSetCC(CondCode Code)796 inline bool isSignedIntSetCC(CondCode Code) { 797 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; 798 } 799 800 /// isUnsignedIntSetCC - Return true if this is a setcc instruction that 801 /// performs an unsigned comparison when used with integer operands. isUnsignedIntSetCC(CondCode Code)802 inline bool isUnsignedIntSetCC(CondCode Code) { 803 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; 804 } 805 806 /// isTrueWhenEqual - Return true if the specified condition returns true if 807 /// the two operands to the condition are equal. Note that if one of the two 808 /// operands is a NaN, this value is meaningless. isTrueWhenEqual(CondCode Cond)809 inline bool isTrueWhenEqual(CondCode Cond) { 810 return ((int)Cond & 1) != 0; 811 } 812 813 /// getUnorderedFlavor - This function returns 0 if the condition is always 814 /// false if an operand is a NaN, 1 if the condition is always true if the 815 /// operand is a NaN, and 2 if the condition is undefined if the operand is a 816 /// NaN. getUnorderedFlavor(CondCode Cond)817 inline unsigned getUnorderedFlavor(CondCode Cond) { 818 return ((int)Cond >> 3) & 3; 819 } 820 821 /// getSetCCInverse - Return the operation corresponding to !(X op Y), where 822 /// 'op' is a valid SetCC operation. 823 CondCode getSetCCInverse(CondCode Operation, bool isInteger); 824 825 /// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 826 /// when given the operation for (X op Y). 827 CondCode getSetCCSwappedOperands(CondCode Operation); 828 829 /// getSetCCOrOperation - Return the result of a logical OR between different 830 /// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This 831 /// function returns SETCC_INVALID if it is not possible to represent the 832 /// resultant comparison. 833 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger); 834 835 /// getSetCCAndOperation - Return the result of a logical AND between 836 /// different comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 837 /// function returns SETCC_INVALID if it is not possible to represent the 838 /// resultant comparison. 839 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger); 840 841 //===--------------------------------------------------------------------===// 842 /// CvtCode enum - This enum defines the various converts CONVERT_RNDSAT 843 /// supports. 844 enum CvtCode { 845 CVT_FF, /// Float from Float 846 CVT_FS, /// Float from Signed 847 CVT_FU, /// Float from Unsigned 848 CVT_SF, /// Signed from Float 849 CVT_UF, /// Unsigned from Float 850 CVT_SS, /// Signed from Signed 851 CVT_SU, /// Signed from Unsigned 852 CVT_US, /// Unsigned from Signed 853 CVT_UU, /// Unsigned from Unsigned 854 CVT_INVALID /// Marker - Invalid opcode 855 }; 856 857 } // end llvm::ISD namespace 858 859 } // end llvm namespace 860 861 #endif 862