| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.cpp | 731 void MipsAsmPrinter::EmitInstrRegReg(unsigned Opcode, unsigned Reg1, in EmitInstrRegReg()
750 void MipsAsmPrinter::EmitInstrRegRegReg(unsigned Opcode, unsigned Reg1, in EmitInstrRegRegReg()
760 void MipsAsmPrinter::EmitMovFPIntPair(unsigned MovOpc, unsigned Reg1, in EmitMovFPIntPair()
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| D | Mips16InstrInfo.cpp | 266 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig()
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| D | MipsSEFrameLowering.cpp | 331 unsigned Reg1 = in emitPrologue() local
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 116 unsigned Reg1, bool isKill1, in addRegReg()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 415 unsigned Reg1 = Reg; in lowerCRSpilling() local
459 unsigned Reg1 = Reg; in lowerCRRestore() local
533 unsigned Reg1 = Reg; in lowerCRBitSpilling() local
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| D | PPCInstrInfo.cpp | 251 unsigned Reg1 = MI->getOperand(1).getReg(); in commuteInstruction() local
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 80 bool contains(unsigned Reg1, unsigned Reg2) const { in contains()
525 uint16_t Reg1; variable
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 630 unsigned Reg1 = CSI[idx].getReg(); in spillCalleeSavedRegisters() local
705 unsigned Reg1 = CSI[i].getReg(); in restoreCalleeSavedRegisters() local
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 1322 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); in printVectorListTwo() local
1335 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); in printVectorListTwoSpaced() local
1386 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); in printVectorListTwoAllLanes() local
1431 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); in printVectorListTwoSpacedAllLanes() local
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AsmBackend.cpp | 408 unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true); in generateCompactUnwindEncoding() local
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| /external/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 464 unsigned Reg1, unsigned Reg2) { in createRegSequence()
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| D | Thumb2SizeReduction.cpp | 642 unsigned Reg1 = MI->getOperand(1).getReg(); in ReduceTo2Addr() local
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| D | ARMFastISel.cpp | 2779 unsigned Reg1 = getRegForValue(Src1Value); in SelectShift() local
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| D | ARMBaseInstrInfo.cpp | 2590 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); in FoldImmediate() local
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| D | ARMISelDAGToDAG.cpp | 3366 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg(); in SelectInlineAsm() local
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 81 bool contains(unsigned Reg1, unsigned Reg2) const { in contains()
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| /external/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 137 unsigned Reg1 = MI->getOperand(Idx1).getReg(); in commuteInstruction() local
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| D | AggressiveAntiDepBreaker.cpp | 80 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) in UnionGroups()
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| /external/llvm/lib/MC/ |
| D | MCDwarf.cpp | 1091 unsigned Reg1 = Instr.getRegister(); in EmitCFIInstruction() local
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 1128 CodeGenRegister *Reg1 = Registers[i]; in computeComposites() local
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 5529 unsigned Reg1 = Op1.getReg(); in ParseInstruction() local
|