| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ExpandPseudoInsts.cpp | 75 const unsigned ShiftAmt = ToIdx * 16; in replicateChunk() local
92 const unsigned ShiftAmt = ChunkIdx * 16; in tryOrrMovk() local
173 unsigned ShiftAmt = 0; in tryToreplicateChunks() local
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| D | AArch64ISelDAGToDAG.cpp | 239 unsigned ShiftAmt; in SelectArithImmed() local
1646 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue); in getUsefulBitsFromOrWithShiftedReg() local
1654 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue); in getUsefulBitsFromOrWithShiftedReg() local
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| /external/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineSimplifyDemanded.cpp | 609 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); in SimplifyDemandedUseBits() local
633 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); in SimplifyDemandedUseBits() local
674 uint32_t ShiftAmt = SA->getLimitedValue(BitWidth-1); in SimplifyDemandedUseBits() local
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| D | InstCombineCasts.cpp | 572 uint32_t ShiftAmt = KnownZeroMask.logBase2(); in transformZExtICmp() local
712 uint64_t ShiftAmt = Amt->getZExtValue(); in CanEvaluateZExtd() local
941 unsigned ShiftAmt = KnownZeroMask.countTrailingZeros(); in transformSExtICmp() local
955 unsigned ShiftAmt = KnownZeroMask.countLeadingZeros(); in transformSExtICmp() local
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| /external/llvm/lib/Analysis/ |
| D | ValueTracking.cpp | 478 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth); in computeKnownBits() local
490 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth); in computeKnownBits() local
505 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); in computeKnownBits() local
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| D | ConstantFolding.cpp | 176 unsigned ShiftAmt = isLittleEndian ? 0 : SrcBitSize*(Ratio-1); in FoldBitCast() local
208 unsigned ShiftAmt = isLittleEndian ? 0 : DstBitSize*(Ratio-1); in FoldBitCast() local
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| /external/clang/lib/CodeGen/ |
| D | CGBuiltin.cpp | 1770 int ShiftAmt = cast<ConstantInt>(Shift)->getSExtValue(); in EmitNeonRShiftImm() local
2576 Constant *ShiftAmt = ConstantInt::get(SrcTy->getElementType(), in EmitCommonNeonBuiltinExpr() local
2887 Constant *ShiftAmt = ConstantInt::get(SrcTy->getElementType(), in EmitCommonNeonBuiltinExpr() local
4368 uint64_t ShiftAmt = Amt->getZExtValue(); in EmitAArch64BuiltinExpr() local
4385 uint64_t ShiftAmt = Amt->getZExtValue(); in EmitAArch64BuiltinExpr() local
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 806 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy); in SimplifyDemandedBits() local
2853 unsigned ShiftAmt = VT.getSizeInBits() - HiLoVT.getSizeInBits(); in expandMUL() local
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| D | DAGCombiner.cpp | 4186 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); in visitSRA() local
4344 uint64_t ShiftAmt = N1C->getZExtValue(); in visitSRL() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMCodeEmitter.cpp | 1413 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm(); in emitMiscArithInstruction() local
1456 unsigned ShiftAmt = MI.getOperand(3).getImm(); in emitSaturateInstruction() local
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| D | ARMISelLowering.cpp | 8054 unsigned ShiftAmt = countTrailingZeros<uint64_t>(MulAmt); in PerformMULCombine() local
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 839 unsigned ShiftAmt = Shift.getConstantOperandVal(1); in FoldMaskedShiftToScaledMask() local
899 unsigned ShiftAmt = Shift.getConstantOperandVal(1); in FoldMaskAndShiftToScale() local
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| D | X86ISelLowering.cpp | 13368 SDValue SrcOp, uint64_t ShiftAmt, in getTargetVShiftByConstNode()
15216 uint64_t ShiftAmt = ShiftConst->getZExtValue(); in LowerScalarImmediateShift() local
15337 uint64_t ShiftAmt = 0; in LowerScalarImmediateShift() local
20303 APInt ShiftAmt = AmtSplat->getAPIntValue(); in performShiftToAllZeros() local
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUISelLowering.cpp | 1197 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in LowerLOAD() local
1255 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in LowerSTORE() local
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| D | SIISelLowering.cpp | 972 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in LowerSTORE() local
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelDAGToDAG.cpp | 3338 uint64_t ShiftAmt = ShiftCnst->getZExtValue(); in SelectBFE() local
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| D | NVPTXISelLowering.cpp | 2960 APInt ShiftAmt = ShlRHS->getAPIntValue(); in TryMULWIDECombine() local
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| /external/llvm/lib/ExecutionEngine/Interpreter/ |
| D | Execution.cpp | 1562 unsigned ShiftAmt = isLittleEndian ? 0 : SrcBitSize * (Ratio - 1); in executeBitCastInst() local
1578 unsigned ShiftAmt = isLittleEndian ? 0 : DstBitSize * (Ratio - 1); in executeBitCastInst() local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 1089 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword() local
1322 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); in emitAtomicCmpSwapPartword() local
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| /external/llvm/lib/Transforms/Scalar/ |
| D | GVN.cpp | 1130 unsigned ShiftAmt; in GetStoreValueForLoad() local
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| /external/llvm/lib/Support/ |
| D | APInt.cpp | 2218 unsigned ShiftAmt = (Radix == 16 ? 4 : (Radix == 8 ? 3 : 1)); in toString() local
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 2735 SDValue ShiftAmt = DAG.getConstant(63, VT); in LowerUMULO_SMULO() local
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| /external/llvm/lib/Transforms/Utils/ |
| D | SimplifyCFG.cpp | 3612 Value *ShiftAmt = Builder.CreateZExtOrTrunc(Index, MapTy, "switch.cast"); in BuildLookup() local
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 3098 uint32_t ShiftAmt = 0, MaxShiftAmt = IsXReg ? 48 : 16; in parseOperand() local
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 968 unsigned ShiftAmt = SVOp->getMaskElt(i); in isVSLDOIShuffleMask() local
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