Searched defs:SubReg0 (Results 1 – 4 of 4) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AdvSIMDScalarPass.cpp | 196 unsigned Src0 = 0, SubReg0; in isProfitableToTransform() local
289 unsigned Src0 = 0, SubReg0; in transformInstruction() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1568 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32); in createGPRPairNode() local
1579 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32); in createSRegPairNode() local
1589 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32); in createDRegPairNode() local
1599 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32); in createQRegPairNode() local
1611 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32); in createQuadSRegsNode() local
1625 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32); in createQuadDRegsNode() local
1639 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32); in createQuadQRegsNode() local
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUISelDAGToDAG.cpp | 337 SDValue RC, SubReg0, SubReg1; in Select() local
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| /external/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 139 unsigned SubReg0 = HasDef ? MI->getOperand(0).getSubReg() : 0; in commuteInstruction() local
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