1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PPC implementation of TargetFrameLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "PPCFrameLowering.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCInstrInfo.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCSubtarget.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineModuleInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/Target/TargetOptions.h"
27
28 using namespace llvm;
29
30 /// VRRegNo - Map from a numbered VR register to its enum value.
31 ///
32 static const uint16_t VRRegNo[] = {
33 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
34 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
35 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
36 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
37 };
38
PPCFrameLowering(const PPCSubtarget & STI)39 PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI)
40 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
41 (STI.hasQPX() || STI.isBGQ()) ? 32 : 16, 0),
42 Subtarget(STI) {}
43
44 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
getCalleeSavedSpillSlots(unsigned & NumEntries) const45 const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots(
46 unsigned &NumEntries) const {
47 if (Subtarget.isDarwinABI()) {
48 NumEntries = 1;
49 if (Subtarget.isPPC64()) {
50 static const SpillSlot darwin64Offsets = {PPC::X31, -8};
51 return &darwin64Offsets;
52 } else {
53 static const SpillSlot darwinOffsets = {PPC::R31, -4};
54 return &darwinOffsets;
55 }
56 }
57
58 // Early exit if not using the SVR4 ABI.
59 if (!Subtarget.isSVR4ABI()) {
60 NumEntries = 0;
61 return nullptr;
62 }
63
64 // Note that the offsets here overlap, but this is fixed up in
65 // processFunctionBeforeFrameFinalized.
66
67 static const SpillSlot Offsets[] = {
68 // Floating-point register save area offsets.
69 {PPC::F31, -8},
70 {PPC::F30, -16},
71 {PPC::F29, -24},
72 {PPC::F28, -32},
73 {PPC::F27, -40},
74 {PPC::F26, -48},
75 {PPC::F25, -56},
76 {PPC::F24, -64},
77 {PPC::F23, -72},
78 {PPC::F22, -80},
79 {PPC::F21, -88},
80 {PPC::F20, -96},
81 {PPC::F19, -104},
82 {PPC::F18, -112},
83 {PPC::F17, -120},
84 {PPC::F16, -128},
85 {PPC::F15, -136},
86 {PPC::F14, -144},
87
88 // General register save area offsets.
89 {PPC::R31, -4},
90 {PPC::R30, -8},
91 {PPC::R29, -12},
92 {PPC::R28, -16},
93 {PPC::R27, -20},
94 {PPC::R26, -24},
95 {PPC::R25, -28},
96 {PPC::R24, -32},
97 {PPC::R23, -36},
98 {PPC::R22, -40},
99 {PPC::R21, -44},
100 {PPC::R20, -48},
101 {PPC::R19, -52},
102 {PPC::R18, -56},
103 {PPC::R17, -60},
104 {PPC::R16, -64},
105 {PPC::R15, -68},
106 {PPC::R14, -72},
107
108 // CR save area offset. We map each of the nonvolatile CR fields
109 // to the slot for CR2, which is the first of the nonvolatile CR
110 // fields to be assigned, so that we only allocate one save slot.
111 // See PPCRegisterInfo::hasReservedSpillSlot() for more information.
112 {PPC::CR2, -4},
113
114 // VRSAVE save area offset.
115 {PPC::VRSAVE, -4},
116
117 // Vector register save area
118 {PPC::V31, -16},
119 {PPC::V30, -32},
120 {PPC::V29, -48},
121 {PPC::V28, -64},
122 {PPC::V27, -80},
123 {PPC::V26, -96},
124 {PPC::V25, -112},
125 {PPC::V24, -128},
126 {PPC::V23, -144},
127 {PPC::V22, -160},
128 {PPC::V21, -176},
129 {PPC::V20, -192}};
130
131 static const SpillSlot Offsets64[] = {
132 // Floating-point register save area offsets.
133 {PPC::F31, -8},
134 {PPC::F30, -16},
135 {PPC::F29, -24},
136 {PPC::F28, -32},
137 {PPC::F27, -40},
138 {PPC::F26, -48},
139 {PPC::F25, -56},
140 {PPC::F24, -64},
141 {PPC::F23, -72},
142 {PPC::F22, -80},
143 {PPC::F21, -88},
144 {PPC::F20, -96},
145 {PPC::F19, -104},
146 {PPC::F18, -112},
147 {PPC::F17, -120},
148 {PPC::F16, -128},
149 {PPC::F15, -136},
150 {PPC::F14, -144},
151
152 // General register save area offsets.
153 {PPC::X31, -8},
154 {PPC::X30, -16},
155 {PPC::X29, -24},
156 {PPC::X28, -32},
157 {PPC::X27, -40},
158 {PPC::X26, -48},
159 {PPC::X25, -56},
160 {PPC::X24, -64},
161 {PPC::X23, -72},
162 {PPC::X22, -80},
163 {PPC::X21, -88},
164 {PPC::X20, -96},
165 {PPC::X19, -104},
166 {PPC::X18, -112},
167 {PPC::X17, -120},
168 {PPC::X16, -128},
169 {PPC::X15, -136},
170 {PPC::X14, -144},
171
172 // VRSAVE save area offset.
173 {PPC::VRSAVE, -4},
174
175 // Vector register save area
176 {PPC::V31, -16},
177 {PPC::V30, -32},
178 {PPC::V29, -48},
179 {PPC::V28, -64},
180 {PPC::V27, -80},
181 {PPC::V26, -96},
182 {PPC::V25, -112},
183 {PPC::V24, -128},
184 {PPC::V23, -144},
185 {PPC::V22, -160},
186 {PPC::V21, -176},
187 {PPC::V20, -192}};
188
189 if (Subtarget.isPPC64()) {
190 NumEntries = array_lengthof(Offsets64);
191
192 return Offsets64;
193 } else {
194 NumEntries = array_lengthof(Offsets);
195
196 return Offsets;
197 }
198 }
199
200 /// RemoveVRSaveCode - We have found that this function does not need any code
201 /// to manipulate the VRSAVE register, even though it uses vector registers.
202 /// This can happen when the only registers used are known to be live in or out
203 /// of the function. Remove all of the VRSAVE related code from the function.
204 /// FIXME: The removal of the code results in a compile failure at -O0 when the
205 /// function contains a function call, as the GPR containing original VRSAVE
206 /// contents is spilled and reloaded around the call. Without the prolog code,
207 /// the spill instruction refers to an undefined register. This code needs
208 /// to account for all uses of that GPR.
RemoveVRSaveCode(MachineInstr * MI)209 static void RemoveVRSaveCode(MachineInstr *MI) {
210 MachineBasicBlock *Entry = MI->getParent();
211 MachineFunction *MF = Entry->getParent();
212
213 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
214 MachineBasicBlock::iterator MBBI = MI;
215 ++MBBI;
216 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
217 MBBI->eraseFromParent();
218
219 bool RemovedAllMTVRSAVEs = true;
220 // See if we can find and remove the MTVRSAVE instruction from all of the
221 // epilog blocks.
222 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
223 // If last instruction is a return instruction, add an epilogue
224 if (!I->empty() && I->back().isReturn()) {
225 bool FoundIt = false;
226 for (MBBI = I->end(); MBBI != I->begin(); ) {
227 --MBBI;
228 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
229 MBBI->eraseFromParent(); // remove it.
230 FoundIt = true;
231 break;
232 }
233 }
234 RemovedAllMTVRSAVEs &= FoundIt;
235 }
236 }
237
238 // If we found and removed all MTVRSAVE instructions, remove the read of
239 // VRSAVE as well.
240 if (RemovedAllMTVRSAVEs) {
241 MBBI = MI;
242 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
243 --MBBI;
244 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
245 MBBI->eraseFromParent();
246 }
247
248 // Finally, nuke the UPDATE_VRSAVE.
249 MI->eraseFromParent();
250 }
251
252 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
253 // instruction selector. Based on the vector registers that have been used,
254 // transform this into the appropriate ORI instruction.
HandleVRSaveUpdate(MachineInstr * MI,const TargetInstrInfo & TII)255 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
256 MachineFunction *MF = MI->getParent()->getParent();
257 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
258 DebugLoc dl = MI->getDebugLoc();
259
260 unsigned UsedRegMask = 0;
261 for (unsigned i = 0; i != 32; ++i)
262 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
263 UsedRegMask |= 1 << (31-i);
264
265 // Live in and live out values already must be in the mask, so don't bother
266 // marking them.
267 for (MachineRegisterInfo::livein_iterator
268 I = MF->getRegInfo().livein_begin(),
269 E = MF->getRegInfo().livein_end(); I != E; ++I) {
270 unsigned RegNo = TRI->getEncodingValue(I->first);
271 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
272 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
273 }
274
275 // Live out registers appear as use operands on return instructions.
276 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
277 UsedRegMask != 0 && BI != BE; ++BI) {
278 const MachineBasicBlock &MBB = *BI;
279 if (MBB.empty() || !MBB.back().isReturn())
280 continue;
281 const MachineInstr &Ret = MBB.back();
282 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
283 const MachineOperand &MO = Ret.getOperand(I);
284 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
285 continue;
286 unsigned RegNo = TRI->getEncodingValue(MO.getReg());
287 UsedRegMask &= ~(1 << (31-RegNo));
288 }
289 }
290
291 // If no registers are used, turn this into a copy.
292 if (UsedRegMask == 0) {
293 // Remove all VRSAVE code.
294 RemoveVRSaveCode(MI);
295 return;
296 }
297
298 unsigned SrcReg = MI->getOperand(1).getReg();
299 unsigned DstReg = MI->getOperand(0).getReg();
300
301 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
302 if (DstReg != SrcReg)
303 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
304 .addReg(SrcReg)
305 .addImm(UsedRegMask);
306 else
307 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
308 .addReg(SrcReg, RegState::Kill)
309 .addImm(UsedRegMask);
310 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
311 if (DstReg != SrcReg)
312 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
313 .addReg(SrcReg)
314 .addImm(UsedRegMask >> 16);
315 else
316 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
317 .addReg(SrcReg, RegState::Kill)
318 .addImm(UsedRegMask >> 16);
319 } else {
320 if (DstReg != SrcReg)
321 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
322 .addReg(SrcReg)
323 .addImm(UsedRegMask >> 16);
324 else
325 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
326 .addReg(SrcReg, RegState::Kill)
327 .addImm(UsedRegMask >> 16);
328
329 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
330 .addReg(DstReg, RegState::Kill)
331 .addImm(UsedRegMask & 0xFFFF);
332 }
333
334 // Remove the old UPDATE_VRSAVE instruction.
335 MI->eraseFromParent();
336 }
337
spillsCR(const MachineFunction & MF)338 static bool spillsCR(const MachineFunction &MF) {
339 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
340 return FuncInfo->isCRSpilled();
341 }
342
spillsVRSAVE(const MachineFunction & MF)343 static bool spillsVRSAVE(const MachineFunction &MF) {
344 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
345 return FuncInfo->isVRSAVESpilled();
346 }
347
hasSpills(const MachineFunction & MF)348 static bool hasSpills(const MachineFunction &MF) {
349 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
350 return FuncInfo->hasSpills();
351 }
352
hasNonRISpills(const MachineFunction & MF)353 static bool hasNonRISpills(const MachineFunction &MF) {
354 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
355 return FuncInfo->hasNonRISpills();
356 }
357
358 /// determineFrameLayout - Determine the size of the frame and maximum call
359 /// frame size.
determineFrameLayout(MachineFunction & MF,bool UpdateMF,bool UseEstimate) const360 unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF,
361 bool UpdateMF,
362 bool UseEstimate) const {
363 MachineFrameInfo *MFI = MF.getFrameInfo();
364
365 // Get the number of bytes to allocate from the FrameInfo
366 unsigned FrameSize =
367 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize();
368
369 // Get stack alignments. The frame must be aligned to the greatest of these:
370 unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI
371 unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame
372 unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
373
374 const PPCRegisterInfo *RegInfo =
375 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
376
377 // If we are a leaf function, and use up to 224 bytes of stack space,
378 // don't have a frame pointer, calls, or dynamic alloca then we do not need
379 // to adjust the stack pointer (we fit in the Red Zone).
380 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate
381 // stackless code if all local vars are reg-allocated.
382 bool DisableRedZone = MF.getFunction()->getAttributes().
383 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone);
384 if (!DisableRedZone &&
385 (Subtarget.isPPC64() || // 32-bit SVR4, no stack-
386 !Subtarget.isSVR4ABI() || // allocated locals.
387 FrameSize == 0) &&
388 FrameSize <= 224 && // Fits in red zone.
389 !MFI->hasVarSizedObjects() && // No dynamic alloca.
390 !MFI->adjustsStack() && // No calls.
391 !RegInfo->hasBasePointer(MF)) { // No special alignment.
392 // No need for frame
393 if (UpdateMF)
394 MFI->setStackSize(0);
395 return 0;
396 }
397
398 // Get the maximum call frame size of all the calls.
399 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
400
401 // Maximum call frame needs to be at least big enough for linkage area.
402 unsigned minCallFrameSize = getLinkageSize(Subtarget.isPPC64(),
403 Subtarget.isDarwinABI());
404 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
405
406 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
407 // that allocations will be aligned.
408 if (MFI->hasVarSizedObjects())
409 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
410
411 // Update maximum call frame size.
412 if (UpdateMF)
413 MFI->setMaxCallFrameSize(maxCallFrameSize);
414
415 // Include call frame size in total.
416 FrameSize += maxCallFrameSize;
417
418 // Make sure the frame is aligned.
419 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
420
421 // Update frame info.
422 if (UpdateMF)
423 MFI->setStackSize(FrameSize);
424
425 return FrameSize;
426 }
427
428 // hasFP - Return true if the specified function actually has a dedicated frame
429 // pointer register.
hasFP(const MachineFunction & MF) const430 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const {
431 const MachineFrameInfo *MFI = MF.getFrameInfo();
432 // FIXME: This is pretty much broken by design: hasFP() might be called really
433 // early, before the stack layout was calculated and thus hasFP() might return
434 // true or false here depending on the time of call.
435 return (MFI->getStackSize()) && needsFP(MF);
436 }
437
438 // needsFP - Return true if the specified function should have a dedicated frame
439 // pointer register. This is true if the function has variable sized allocas or
440 // if frame pointer elimination is disabled.
needsFP(const MachineFunction & MF) const441 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
442 const MachineFrameInfo *MFI = MF.getFrameInfo();
443
444 // Naked functions have no stack frame pushed, so we don't have a frame
445 // pointer.
446 if (MF.getFunction()->getAttributes().hasAttribute(
447 AttributeSet::FunctionIndex, Attribute::Naked))
448 return false;
449
450 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
451 MFI->hasVarSizedObjects() ||
452 (MF.getTarget().Options.GuaranteedTailCallOpt &&
453 MF.getInfo<PPCFunctionInfo>()->hasFastCall());
454 }
455
replaceFPWithRealFP(MachineFunction & MF) const456 void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const {
457 bool is31 = needsFP(MF);
458 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
459 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
460
461 const PPCRegisterInfo *RegInfo =
462 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
463 bool HasBP = RegInfo->hasBasePointer(MF);
464 unsigned BPReg = HasBP ? (unsigned) PPC::R30 : FPReg;
465 unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg;
466
467 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
468 BI != BE; ++BI)
469 for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
470 --MBBI;
471 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
472 MachineOperand &MO = MBBI->getOperand(I);
473 if (!MO.isReg())
474 continue;
475
476 switch (MO.getReg()) {
477 case PPC::FP:
478 MO.setReg(FPReg);
479 break;
480 case PPC::FP8:
481 MO.setReg(FP8Reg);
482 break;
483 case PPC::BP:
484 MO.setReg(BPReg);
485 break;
486 case PPC::BP8:
487 MO.setReg(BP8Reg);
488 break;
489
490 }
491 }
492 }
493 }
494
emitPrologue(MachineFunction & MF) const495 void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
496 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
497 MachineBasicBlock::iterator MBBI = MBB.begin();
498 MachineFrameInfo *MFI = MF.getFrameInfo();
499 const PPCInstrInfo &TII =
500 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
501 const PPCRegisterInfo *RegInfo =
502 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
503
504 MachineModuleInfo &MMI = MF.getMMI();
505 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
506 DebugLoc dl;
507 bool needsFrameMoves = MMI.hasDebugInfo() ||
508 MF.getFunction()->needsUnwindTableEntry();
509
510 // Get processor type.
511 bool isPPC64 = Subtarget.isPPC64();
512 // Get the ABI.
513 bool isDarwinABI = Subtarget.isDarwinABI();
514 bool isSVR4ABI = Subtarget.isSVR4ABI();
515 assert((isDarwinABI || isSVR4ABI) &&
516 "Currently only Darwin and SVR4 ABIs are supported for PowerPC.");
517
518 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
519 // process it.
520 if (!isSVR4ABI)
521 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
522 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
523 HandleVRSaveUpdate(MBBI, TII);
524 break;
525 }
526 }
527
528 // Move MBBI back to the beginning of the function.
529 MBBI = MBB.begin();
530
531 // Work out frame sizes.
532 unsigned FrameSize = determineFrameLayout(MF);
533 int NegFrameSize = -FrameSize;
534 if (!isInt<32>(NegFrameSize))
535 llvm_unreachable("Unhandled stack size!");
536
537 if (MFI->isFrameAddressTaken())
538 replaceFPWithRealFP(MF);
539
540 // Check if the link register (LR) must be saved.
541 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
542 bool MustSaveLR = FI->mustSaveLR();
543 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
544 // Do we have a frame pointer and/or base pointer for this function?
545 bool HasFP = hasFP(MF);
546 bool HasBP = RegInfo->hasBasePointer(MF);
547
548 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
549 unsigned BPReg = isPPC64 ? PPC::X30 : PPC::R30;
550 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
551 unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
552 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
553 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
554 // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.)
555 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
556 : PPC::MFLR );
557 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
558 : PPC::STW );
559 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
560 : PPC::STWU );
561 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
562 : PPC::STWUX);
563 const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
564 : PPC::LIS );
565 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
566 : PPC::ORI );
567 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
568 : PPC::OR );
569 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
570 : PPC::SUBFC);
571 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
572 : PPC::SUBFIC);
573
574 // Regarding this assert: Even though LR is saved in the caller's frame (i.e.,
575 // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no
576 // Red Zone, an asynchronous event (a form of "callee") could claim a frame &
577 // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR.
578 assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
579 "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
580
581 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
582
583 int FPOffset = 0;
584 if (HasFP) {
585 if (isSVR4ABI) {
586 MachineFrameInfo *FFI = MF.getFrameInfo();
587 int FPIndex = FI->getFramePointerSaveIndex();
588 assert(FPIndex && "No Frame Pointer Save Slot!");
589 FPOffset = FFI->getObjectOffset(FPIndex);
590 } else {
591 FPOffset =
592 PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
593 }
594 }
595
596 int BPOffset = 0;
597 if (HasBP) {
598 if (isSVR4ABI) {
599 MachineFrameInfo *FFI = MF.getFrameInfo();
600 int BPIndex = FI->getBasePointerSaveIndex();
601 assert(BPIndex && "No Base Pointer Save Slot!");
602 BPOffset = FFI->getObjectOffset(BPIndex);
603 } else {
604 BPOffset =
605 PPCFrameLowering::getBasePointerSaveOffset(isPPC64, isDarwinABI);
606 }
607 }
608
609 // Get stack alignments.
610 unsigned MaxAlign = MFI->getMaxAlignment();
611 if (HasBP && MaxAlign > 1)
612 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
613 "Invalid alignment!");
614
615 // Frames of 32KB & larger require special handling because they cannot be
616 // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
617 bool isLargeFrame = !isInt<16>(NegFrameSize);
618
619 if (MustSaveLR)
620 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
621
622 assert((isPPC64 || MustSaveCRs.empty()) &&
623 "Prologue CR saving supported only in 64-bit mode");
624
625 if (!MustSaveCRs.empty()) { // will only occur for PPC64
626 MachineInstrBuilder MIB =
627 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg);
628 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
629 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
630 }
631
632 if (HasFP)
633 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
634 BuildMI(MBB, MBBI, dl, StoreInst)
635 .addReg(FPReg)
636 .addImm(FPOffset)
637 .addReg(SPReg);
638
639 if (HasBP)
640 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
641 BuildMI(MBB, MBBI, dl, StoreInst)
642 .addReg(BPReg)
643 .addImm(BPOffset)
644 .addReg(SPReg);
645
646 if (MustSaveLR)
647 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
648 BuildMI(MBB, MBBI, dl, StoreInst)
649 .addReg(ScratchReg)
650 .addImm(LROffset)
651 .addReg(SPReg);
652
653 if (!MustSaveCRs.empty()) // will only occur for PPC64
654 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
655 .addReg(TempReg, getKillRegState(true))
656 .addImm(8)
657 .addReg(SPReg);
658
659 // Skip the rest if this is a leaf function & all spills fit in the Red Zone.
660 if (!FrameSize) return;
661
662 // Adjust stack pointer: r1 += NegFrameSize.
663 // If there is a preferred stack alignment, align R1 now
664
665 if (HasBP) {
666 // Save a copy of r1 as the base pointer.
667 BuildMI(MBB, MBBI, dl, OrInst, BPReg)
668 .addReg(SPReg)
669 .addReg(SPReg);
670 }
671
672 if (HasBP && MaxAlign > 1) {
673 if (isPPC64)
674 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
675 .addReg(SPReg)
676 .addImm(0)
677 .addImm(64 - Log2_32(MaxAlign));
678 else // PPC32...
679 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
680 .addReg(SPReg)
681 .addImm(0)
682 .addImm(32 - Log2_32(MaxAlign))
683 .addImm(31);
684 if (!isLargeFrame) {
685 BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
686 .addReg(ScratchReg, RegState::Kill)
687 .addImm(NegFrameSize);
688 } else {
689 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
690 .addImm(NegFrameSize >> 16);
691 BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
692 .addReg(TempReg, RegState::Kill)
693 .addImm(NegFrameSize & 0xFFFF);
694 BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
695 .addReg(ScratchReg, RegState::Kill)
696 .addReg(TempReg, RegState::Kill);
697 }
698 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
699 .addReg(SPReg, RegState::Kill)
700 .addReg(SPReg)
701 .addReg(ScratchReg);
702
703 } else if (!isLargeFrame) {
704 BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg)
705 .addReg(SPReg)
706 .addImm(NegFrameSize)
707 .addReg(SPReg);
708
709 } else {
710 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
711 .addImm(NegFrameSize >> 16);
712 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
713 .addReg(ScratchReg, RegState::Kill)
714 .addImm(NegFrameSize & 0xFFFF);
715 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
716 .addReg(SPReg, RegState::Kill)
717 .addReg(SPReg)
718 .addReg(ScratchReg);
719 }
720
721 // Add the "machine moves" for the instructions we generated above, but in
722 // reverse order.
723 if (needsFrameMoves) {
724 // Show update of SP.
725 assert(NegFrameSize);
726 unsigned CFIIndex = MMI.addFrameInst(
727 MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize));
728 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
729 .addCFIIndex(CFIIndex);
730
731 if (HasFP) {
732 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
733 CFIIndex = MMI.addFrameInst(
734 MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
735 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
736 .addCFIIndex(CFIIndex);
737 }
738
739 if (HasBP) {
740 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
741 CFIIndex = MMI.addFrameInst(
742 MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
743 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
744 .addCFIIndex(CFIIndex);
745 }
746
747 if (MustSaveLR) {
748 unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
749 CFIIndex = MMI.addFrameInst(
750 MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
751 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
752 .addCFIIndex(CFIIndex);
753 }
754 }
755
756 // If there is a frame pointer, copy R1 into R31
757 if (HasFP) {
758 BuildMI(MBB, MBBI, dl, OrInst, FPReg)
759 .addReg(SPReg)
760 .addReg(SPReg);
761
762 if (needsFrameMoves) {
763 // Mark effective beginning of when frame pointer is ready.
764 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
765 unsigned CFIIndex = MMI.addFrameInst(
766 MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
767
768 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
769 .addCFIIndex(CFIIndex);
770 }
771 }
772
773 if (needsFrameMoves) {
774 // Add callee saved registers to move list.
775 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
776 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
777 unsigned Reg = CSI[I].getReg();
778 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
779
780 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
781 // subregisters of CR2. We just need to emit a move of CR2.
782 if (PPC::CRBITRCRegClass.contains(Reg))
783 continue;
784
785 // For SVR4, don't emit a move for the CR spill slot if we haven't
786 // spilled CRs.
787 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
788 && MustSaveCRs.empty())
789 continue;
790
791 // For 64-bit SVR4 when we have spilled CRs, the spill location
792 // is SP+8, not a frame-relative slot.
793 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
794 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
795 nullptr, MRI->getDwarfRegNum(PPC::CR2, true), 8));
796 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
797 .addCFIIndex(CFIIndex);
798 continue;
799 }
800
801 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
802 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
803 nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
804 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
805 .addCFIIndex(CFIIndex);
806 }
807 }
808 }
809
emitEpilogue(MachineFunction & MF,MachineBasicBlock & MBB) const810 void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
811 MachineBasicBlock &MBB) const {
812 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
813 assert(MBBI != MBB.end() && "Returning block has no terminator");
814 const PPCInstrInfo &TII =
815 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
816 const PPCRegisterInfo *RegInfo =
817 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
818
819 unsigned RetOpcode = MBBI->getOpcode();
820 DebugLoc dl;
821
822 assert((RetOpcode == PPC::BLR ||
823 RetOpcode == PPC::TCRETURNri ||
824 RetOpcode == PPC::TCRETURNdi ||
825 RetOpcode == PPC::TCRETURNai ||
826 RetOpcode == PPC::TCRETURNri8 ||
827 RetOpcode == PPC::TCRETURNdi8 ||
828 RetOpcode == PPC::TCRETURNai8) &&
829 "Can only insert epilog into returning blocks");
830
831 // Get alignment info so we know how to restore the SP.
832 const MachineFrameInfo *MFI = MF.getFrameInfo();
833
834 // Get the number of bytes allocated from the FrameInfo.
835 int FrameSize = MFI->getStackSize();
836
837 // Get processor type.
838 bool isPPC64 = Subtarget.isPPC64();
839 // Get the ABI.
840 bool isDarwinABI = Subtarget.isDarwinABI();
841 bool isSVR4ABI = Subtarget.isSVR4ABI();
842
843 // Check if the link register (LR) has been saved.
844 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
845 bool MustSaveLR = FI->mustSaveLR();
846 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
847 // Do we have a frame pointer and/or base pointer for this function?
848 bool HasFP = hasFP(MF);
849 bool HasBP = RegInfo->hasBasePointer(MF);
850
851 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
852 unsigned BPReg = isPPC64 ? PPC::X30 : PPC::R30;
853 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
854 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
855 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
856 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
857 : PPC::MTLR );
858 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
859 : PPC::LWZ );
860 const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
861 : PPC::LIS );
862 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
863 : PPC::ORI );
864 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
865 : PPC::ADDI );
866 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
867 : PPC::ADD4 );
868
869 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
870
871 int FPOffset = 0;
872 if (HasFP) {
873 if (isSVR4ABI) {
874 MachineFrameInfo *FFI = MF.getFrameInfo();
875 int FPIndex = FI->getFramePointerSaveIndex();
876 assert(FPIndex && "No Frame Pointer Save Slot!");
877 FPOffset = FFI->getObjectOffset(FPIndex);
878 } else {
879 FPOffset =
880 PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
881 }
882 }
883
884 int BPOffset = 0;
885 if (HasBP) {
886 if (isSVR4ABI) {
887 MachineFrameInfo *FFI = MF.getFrameInfo();
888 int BPIndex = FI->getBasePointerSaveIndex();
889 assert(BPIndex && "No Base Pointer Save Slot!");
890 BPOffset = FFI->getObjectOffset(BPIndex);
891 } else {
892 BPOffset =
893 PPCFrameLowering::getBasePointerSaveOffset(isPPC64, isDarwinABI);
894 }
895 }
896
897 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
898 RetOpcode == PPC::TCRETURNdi ||
899 RetOpcode == PPC::TCRETURNai ||
900 RetOpcode == PPC::TCRETURNri8 ||
901 RetOpcode == PPC::TCRETURNdi8 ||
902 RetOpcode == PPC::TCRETURNai8;
903
904 if (UsesTCRet) {
905 int MaxTCRetDelta = FI->getTailCallSPDelta();
906 MachineOperand &StackAdjust = MBBI->getOperand(1);
907 assert(StackAdjust.isImm() && "Expecting immediate value.");
908 // Adjust stack pointer.
909 int StackAdj = StackAdjust.getImm();
910 int Delta = StackAdj - MaxTCRetDelta;
911 assert((Delta >= 0) && "Delta must be positive");
912 if (MaxTCRetDelta>0)
913 FrameSize += (StackAdj +Delta);
914 else
915 FrameSize += StackAdj;
916 }
917
918 // Frames of 32KB & larger require special handling because they cannot be
919 // indexed into with a simple LD/LWZ immediate offset operand.
920 bool isLargeFrame = !isInt<16>(FrameSize);
921
922 if (FrameSize) {
923 // In the prologue, the loaded (or persistent) stack pointer value is offset
924 // by the STDU/STDUX/STWU/STWUX instruction. Add this offset back now.
925
926 // If this function contained a fastcc call and GuaranteedTailCallOpt is
927 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
928 // call which invalidates the stack pointer value in SP(0). So we use the
929 // value of R31 in this case.
930 if (FI->hasFastCall()) {
931 assert(HasFP && "Expecting a valid frame pointer.");
932 if (!isLargeFrame) {
933 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
934 .addReg(FPReg).addImm(FrameSize);
935 } else {
936 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
937 .addImm(FrameSize >> 16);
938 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
939 .addReg(ScratchReg, RegState::Kill)
940 .addImm(FrameSize & 0xFFFF);
941 BuildMI(MBB, MBBI, dl, AddInst)
942 .addReg(SPReg)
943 .addReg(FPReg)
944 .addReg(ScratchReg);
945 }
946 } else if (!isLargeFrame && !HasBP && !MFI->hasVarSizedObjects()) {
947 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
948 .addReg(SPReg)
949 .addImm(FrameSize);
950 } else {
951 BuildMI(MBB, MBBI, dl, LoadInst, SPReg)
952 .addImm(0)
953 .addReg(SPReg);
954 }
955
956 }
957
958 if (MustSaveLR)
959 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
960 .addImm(LROffset)
961 .addReg(SPReg);
962
963 assert((isPPC64 || MustSaveCRs.empty()) &&
964 "Epilogue CR restoring supported only in 64-bit mode");
965
966 if (!MustSaveCRs.empty()) // will only occur for PPC64
967 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
968 .addImm(8)
969 .addReg(SPReg);
970
971 if (HasFP)
972 BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
973 .addImm(FPOffset)
974 .addReg(SPReg);
975
976 if (HasBP)
977 BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
978 .addImm(BPOffset)
979 .addReg(SPReg);
980
981 if (!MustSaveCRs.empty()) // will only occur for PPC64
982 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
983 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
984 .addReg(TempReg, getKillRegState(i == e-1));
985
986 if (MustSaveLR)
987 BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg);
988
989 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
990 // call optimization
991 if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR &&
992 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
993 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
994 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
995
996 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
997 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
998 .addReg(SPReg).addImm(CallerAllocatedAmt);
999 } else {
1000 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1001 .addImm(CallerAllocatedAmt >> 16);
1002 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1003 .addReg(ScratchReg, RegState::Kill)
1004 .addImm(CallerAllocatedAmt & 0xFFFF);
1005 BuildMI(MBB, MBBI, dl, AddInst)
1006 .addReg(SPReg)
1007 .addReg(FPReg)
1008 .addReg(ScratchReg);
1009 }
1010 } else if (RetOpcode == PPC::TCRETURNdi) {
1011 MBBI = MBB.getLastNonDebugInstr();
1012 MachineOperand &JumpTarget = MBBI->getOperand(0);
1013 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1014 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1015 } else if (RetOpcode == PPC::TCRETURNri) {
1016 MBBI = MBB.getLastNonDebugInstr();
1017 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1018 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1019 } else if (RetOpcode == PPC::TCRETURNai) {
1020 MBBI = MBB.getLastNonDebugInstr();
1021 MachineOperand &JumpTarget = MBBI->getOperand(0);
1022 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1023 } else if (RetOpcode == PPC::TCRETURNdi8) {
1024 MBBI = MBB.getLastNonDebugInstr();
1025 MachineOperand &JumpTarget = MBBI->getOperand(0);
1026 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1027 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1028 } else if (RetOpcode == PPC::TCRETURNri8) {
1029 MBBI = MBB.getLastNonDebugInstr();
1030 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1031 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1032 } else if (RetOpcode == PPC::TCRETURNai8) {
1033 MBBI = MBB.getLastNonDebugInstr();
1034 MachineOperand &JumpTarget = MBBI->getOperand(0);
1035 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
1036 }
1037 }
1038
1039 /// MustSaveLR - Return true if this function requires that we save the LR
1040 /// register onto the stack in the prolog and restore it in the epilog of the
1041 /// function.
MustSaveLR(const MachineFunction & MF,unsigned LR)1042 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
1043 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
1044
1045 // We need a save/restore of LR if there is any def of LR (which is
1046 // defined by calls, including the PIC setup sequence), or if there is
1047 // some use of the LR stack slot (e.g. for builtin_return_address).
1048 // (LR comes in 32 and 64 bit versions.)
1049 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
1050 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
1051 }
1052
1053 void
processFunctionBeforeCalleeSavedScan(MachineFunction & MF,RegScavenger *) const1054 PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1055 RegScavenger *) const {
1056 const PPCRegisterInfo *RegInfo =
1057 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
1058
1059 // Save and clear the LR state.
1060 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1061 unsigned LR = RegInfo->getRARegister();
1062 FI->setMustSaveLR(MustSaveLR(MF, LR));
1063 MachineRegisterInfo &MRI = MF.getRegInfo();
1064 MRI.setPhysRegUnused(LR);
1065
1066 // Save R31 if necessary
1067 int FPSI = FI->getFramePointerSaveIndex();
1068 bool isPPC64 = Subtarget.isPPC64();
1069 bool isDarwinABI = Subtarget.isDarwinABI();
1070 MachineFrameInfo *MFI = MF.getFrameInfo();
1071
1072 // If the frame pointer save index hasn't been defined yet.
1073 if (!FPSI && needsFP(MF)) {
1074 // Find out what the fix offset of the frame pointer save area.
1075 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI);
1076 // Allocate the frame index for frame pointer save area.
1077 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
1078 // Save the result.
1079 FI->setFramePointerSaveIndex(FPSI);
1080 }
1081
1082 int BPSI = FI->getBasePointerSaveIndex();
1083 if (!BPSI && RegInfo->hasBasePointer(MF)) {
1084 int BPOffset = getBasePointerSaveOffset(isPPC64, isDarwinABI);
1085 // Allocate the frame index for the base pointer save area.
1086 BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
1087 // Save the result.
1088 FI->setBasePointerSaveIndex(BPSI);
1089 }
1090
1091 // Reserve stack space to move the linkage area to in case of a tail call.
1092 int TCSPDelta = 0;
1093 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1094 (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
1095 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
1096 }
1097
1098 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
1099 // function uses CR 2, 3, or 4.
1100 if (!isPPC64 && !isDarwinABI &&
1101 (MRI.isPhysRegUsed(PPC::CR2) ||
1102 MRI.isPhysRegUsed(PPC::CR3) ||
1103 MRI.isPhysRegUsed(PPC::CR4))) {
1104 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true);
1105 FI->setCRSpillFrameIndex(FrameIdx);
1106 }
1107 }
1108
processFunctionBeforeFrameFinalized(MachineFunction & MF,RegScavenger * RS) const1109 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
1110 RegScavenger *RS) const {
1111 // Early exit if not using the SVR4 ABI.
1112 if (!Subtarget.isSVR4ABI()) {
1113 addScavengingSpillSlot(MF, RS);
1114 return;
1115 }
1116
1117 // Get callee saved register information.
1118 MachineFrameInfo *FFI = MF.getFrameInfo();
1119 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
1120
1121 // Early exit if no callee saved registers are modified!
1122 if (CSI.empty() && !needsFP(MF)) {
1123 addScavengingSpillSlot(MF, RS);
1124 return;
1125 }
1126
1127 unsigned MinGPR = PPC::R31;
1128 unsigned MinG8R = PPC::X31;
1129 unsigned MinFPR = PPC::F31;
1130 unsigned MinVR = PPC::V31;
1131
1132 bool HasGPSaveArea = false;
1133 bool HasG8SaveArea = false;
1134 bool HasFPSaveArea = false;
1135 bool HasVRSAVESaveArea = false;
1136 bool HasVRSaveArea = false;
1137
1138 SmallVector<CalleeSavedInfo, 18> GPRegs;
1139 SmallVector<CalleeSavedInfo, 18> G8Regs;
1140 SmallVector<CalleeSavedInfo, 18> FPRegs;
1141 SmallVector<CalleeSavedInfo, 18> VRegs;
1142
1143 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1144 unsigned Reg = CSI[i].getReg();
1145 if (PPC::GPRCRegClass.contains(Reg)) {
1146 HasGPSaveArea = true;
1147
1148 GPRegs.push_back(CSI[i]);
1149
1150 if (Reg < MinGPR) {
1151 MinGPR = Reg;
1152 }
1153 } else if (PPC::G8RCRegClass.contains(Reg)) {
1154 HasG8SaveArea = true;
1155
1156 G8Regs.push_back(CSI[i]);
1157
1158 if (Reg < MinG8R) {
1159 MinG8R = Reg;
1160 }
1161 } else if (PPC::F8RCRegClass.contains(Reg)) {
1162 HasFPSaveArea = true;
1163
1164 FPRegs.push_back(CSI[i]);
1165
1166 if (Reg < MinFPR) {
1167 MinFPR = Reg;
1168 }
1169 } else if (PPC::CRBITRCRegClass.contains(Reg) ||
1170 PPC::CRRCRegClass.contains(Reg)) {
1171 ; // do nothing, as we already know whether CRs are spilled
1172 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1173 HasVRSAVESaveArea = true;
1174 } else if (PPC::VRRCRegClass.contains(Reg)) {
1175 HasVRSaveArea = true;
1176
1177 VRegs.push_back(CSI[i]);
1178
1179 if (Reg < MinVR) {
1180 MinVR = Reg;
1181 }
1182 } else {
1183 llvm_unreachable("Unknown RegisterClass!");
1184 }
1185 }
1186
1187 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
1188 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
1189
1190 int64_t LowerBound = 0;
1191
1192 // Take into account stack space reserved for tail calls.
1193 int TCSPDelta = 0;
1194 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1195 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
1196 LowerBound = TCSPDelta;
1197 }
1198
1199 // The Floating-point register save area is right below the back chain word
1200 // of the previous stack frame.
1201 if (HasFPSaveArea) {
1202 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
1203 int FI = FPRegs[i].getFrameIdx();
1204
1205 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1206 }
1207
1208 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
1209 }
1210
1211 // Check whether the frame pointer register is allocated. If so, make sure it
1212 // is spilled to the correct offset.
1213 if (needsFP(MF)) {
1214 HasGPSaveArea = true;
1215
1216 int FI = PFI->getFramePointerSaveIndex();
1217 assert(FI && "No Frame Pointer Save Slot!");
1218
1219 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1220 }
1221
1222 const PPCRegisterInfo *RegInfo =
1223 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
1224 if (RegInfo->hasBasePointer(MF)) {
1225 HasGPSaveArea = true;
1226
1227 int FI = PFI->getBasePointerSaveIndex();
1228 assert(FI && "No Base Pointer Save Slot!");
1229
1230 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1231 }
1232
1233 // General register save area starts right below the Floating-point
1234 // register save area.
1235 if (HasGPSaveArea || HasG8SaveArea) {
1236 // Move general register save area spill slots down, taking into account
1237 // the size of the Floating-point register save area.
1238 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
1239 int FI = GPRegs[i].getFrameIdx();
1240
1241 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1242 }
1243
1244 // Move general register save area spill slots down, taking into account
1245 // the size of the Floating-point register save area.
1246 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
1247 int FI = G8Regs[i].getFrameIdx();
1248
1249 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1250 }
1251
1252 unsigned MinReg =
1253 std::min<unsigned>(TRI->getEncodingValue(MinGPR),
1254 TRI->getEncodingValue(MinG8R));
1255
1256 if (Subtarget.isPPC64()) {
1257 LowerBound -= (31 - MinReg + 1) * 8;
1258 } else {
1259 LowerBound -= (31 - MinReg + 1) * 4;
1260 }
1261 }
1262
1263 // For 32-bit only, the CR save area is below the general register
1264 // save area. For 64-bit SVR4, the CR save area is addressed relative
1265 // to the stack pointer and hence does not need an adjustment here.
1266 // Only CR2 (the first nonvolatile spilled) has an associated frame
1267 // index so that we have a single uniform save area.
1268 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
1269 // Adjust the frame index of the CR spill slot.
1270 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1271 unsigned Reg = CSI[i].getReg();
1272
1273 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
1274 // Leave Darwin logic as-is.
1275 || (!Subtarget.isSVR4ABI() &&
1276 (PPC::CRBITRCRegClass.contains(Reg) ||
1277 PPC::CRRCRegClass.contains(Reg)))) {
1278 int FI = CSI[i].getFrameIdx();
1279
1280 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1281 }
1282 }
1283
1284 LowerBound -= 4; // The CR save area is always 4 bytes long.
1285 }
1286
1287 if (HasVRSAVESaveArea) {
1288 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1289 // which have the VRSAVE register class?
1290 // Adjust the frame index of the VRSAVE spill slot.
1291 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1292 unsigned Reg = CSI[i].getReg();
1293
1294 if (PPC::VRSAVERCRegClass.contains(Reg)) {
1295 int FI = CSI[i].getFrameIdx();
1296
1297 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1298 }
1299 }
1300
1301 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1302 }
1303
1304 if (HasVRSaveArea) {
1305 // Insert alignment padding, we need 16-byte alignment.
1306 LowerBound = (LowerBound - 15) & ~(15);
1307
1308 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1309 int FI = VRegs[i].getFrameIdx();
1310
1311 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1312 }
1313 }
1314
1315 addScavengingSpillSlot(MF, RS);
1316 }
1317
1318 void
addScavengingSpillSlot(MachineFunction & MF,RegScavenger * RS) const1319 PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
1320 RegScavenger *RS) const {
1321 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
1322 // a large stack, which will require scavenging a register to materialize a
1323 // large offset.
1324
1325 // We need to have a scavenger spill slot for spills if the frame size is
1326 // large. In case there is no free register for large-offset addressing,
1327 // this slot is used for the necessary emergency spill. Also, we need the
1328 // slot for dynamic stack allocations.
1329
1330 // The scavenger might be invoked if the frame offset does not fit into
1331 // the 16-bit immediate. We don't know the complete frame size here
1332 // because we've not yet computed callee-saved register spills or the
1333 // needed alignment padding.
1334 unsigned StackSize = determineFrameLayout(MF, false, true);
1335 MachineFrameInfo *MFI = MF.getFrameInfo();
1336 if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
1337 hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
1338 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1339 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1340 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
1341 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1342 RC->getAlignment(),
1343 false));
1344
1345 // Might we have over-aligned allocas?
1346 bool HasAlVars = MFI->hasVarSizedObjects() &&
1347 MFI->getMaxAlignment() > getStackAlignment();
1348
1349 // These kinds of spills might need two registers.
1350 if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)
1351 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1352 RC->getAlignment(),
1353 false));
1354
1355 }
1356 }
1357
1358 bool
spillCalleeSavedRegisters(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,const std::vector<CalleeSavedInfo> & CSI,const TargetRegisterInfo * TRI) const1359 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1360 MachineBasicBlock::iterator MI,
1361 const std::vector<CalleeSavedInfo> &CSI,
1362 const TargetRegisterInfo *TRI) const {
1363
1364 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1365 // Return false otherwise to maintain pre-existing behavior.
1366 if (!Subtarget.isSVR4ABI())
1367 return false;
1368
1369 MachineFunction *MF = MBB.getParent();
1370 const PPCInstrInfo &TII =
1371 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1372 DebugLoc DL;
1373 bool CRSpilled = false;
1374 MachineInstrBuilder CRMIB;
1375
1376 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1377 unsigned Reg = CSI[i].getReg();
1378 // Only Darwin actually uses the VRSAVE register, but it can still appear
1379 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1380 // Darwin, ignore it.
1381 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1382 continue;
1383
1384 // CR2 through CR4 are the nonvolatile CR fields.
1385 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1386
1387 // Add the callee-saved register as live-in; it's killed at the spill.
1388 MBB.addLiveIn(Reg);
1389
1390 if (CRSpilled && IsCRField) {
1391 CRMIB.addReg(Reg, RegState::ImplicitKill);
1392 continue;
1393 }
1394
1395 // Insert the spill to the stack frame.
1396 if (IsCRField) {
1397 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
1398 if (Subtarget.isPPC64()) {
1399 // The actual spill will happen at the start of the prologue.
1400 FuncInfo->addMustSaveCR(Reg);
1401 } else {
1402 CRSpilled = true;
1403 FuncInfo->setSpillsCR();
1404
1405 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
1406 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
1407 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
1408 .addReg(Reg, RegState::ImplicitKill);
1409
1410 MBB.insert(MI, CRMIB);
1411 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
1412 .addReg(PPC::R12,
1413 getKillRegState(true)),
1414 CSI[i].getFrameIdx()));
1415 }
1416 } else {
1417 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1418 TII.storeRegToStackSlot(MBB, MI, Reg, true,
1419 CSI[i].getFrameIdx(), RC, TRI);
1420 }
1421 }
1422 return true;
1423 }
1424
1425 static void
restoreCRs(bool isPPC64,bool is31,bool CR2Spilled,bool CR3Spilled,bool CR4Spilled,MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,const std::vector<CalleeSavedInfo> & CSI,unsigned CSIIndex)1426 restoreCRs(bool isPPC64, bool is31,
1427 bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
1428 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1429 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
1430
1431 MachineFunction *MF = MBB.getParent();
1432 const PPCInstrInfo &TII =
1433 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1434 DebugLoc DL;
1435 unsigned RestoreOp, MoveReg;
1436
1437 if (isPPC64)
1438 // This is handled during epilogue generation.
1439 return;
1440 else {
1441 // 32-bit: FP-relative
1442 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
1443 PPC::R12),
1444 CSI[CSIIndex].getFrameIdx()));
1445 RestoreOp = PPC::MTOCRF;
1446 MoveReg = PPC::R12;
1447 }
1448
1449 if (CR2Spilled)
1450 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
1451 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
1452
1453 if (CR3Spilled)
1454 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
1455 .addReg(MoveReg, getKillRegState(!CR4Spilled)));
1456
1457 if (CR4Spilled)
1458 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
1459 .addReg(MoveReg, getKillRegState(true)));
1460 }
1461
1462 void PPCFrameLowering::
eliminateCallFramePseudoInstr(MachineFunction & MF,MachineBasicBlock & MBB,MachineBasicBlock::iterator I) const1463 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1464 MachineBasicBlock::iterator I) const {
1465 const PPCInstrInfo &TII =
1466 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
1467 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1468 I->getOpcode() == PPC::ADJCALLSTACKUP) {
1469 // Add (actually subtract) back the amount the callee popped on return.
1470 if (int CalleeAmt = I->getOperand(1).getImm()) {
1471 bool is64Bit = Subtarget.isPPC64();
1472 CalleeAmt *= -1;
1473 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
1474 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
1475 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
1476 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
1477 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
1478 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
1479 MachineInstr *MI = I;
1480 DebugLoc dl = MI->getDebugLoc();
1481
1482 if (isInt<16>(CalleeAmt)) {
1483 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
1484 .addReg(StackReg, RegState::Kill)
1485 .addImm(CalleeAmt);
1486 } else {
1487 MachineBasicBlock::iterator MBBI = I;
1488 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
1489 .addImm(CalleeAmt >> 16);
1490 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
1491 .addReg(TmpReg, RegState::Kill)
1492 .addImm(CalleeAmt & 0xFFFF);
1493 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
1494 .addReg(StackReg, RegState::Kill)
1495 .addReg(TmpReg);
1496 }
1497 }
1498 }
1499 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
1500 MBB.erase(I);
1501 }
1502
1503 bool
restoreCalleeSavedRegisters(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,const std::vector<CalleeSavedInfo> & CSI,const TargetRegisterInfo * TRI) const1504 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1505 MachineBasicBlock::iterator MI,
1506 const std::vector<CalleeSavedInfo> &CSI,
1507 const TargetRegisterInfo *TRI) const {
1508
1509 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1510 // Return false otherwise to maintain pre-existing behavior.
1511 if (!Subtarget.isSVR4ABI())
1512 return false;
1513
1514 MachineFunction *MF = MBB.getParent();
1515 const PPCInstrInfo &TII =
1516 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1517 bool CR2Spilled = false;
1518 bool CR3Spilled = false;
1519 bool CR4Spilled = false;
1520 unsigned CSIIndex = 0;
1521
1522 // Initialize insertion-point logic; we will be restoring in reverse
1523 // order of spill.
1524 MachineBasicBlock::iterator I = MI, BeforeI = I;
1525 bool AtStart = I == MBB.begin();
1526
1527 if (!AtStart)
1528 --BeforeI;
1529
1530 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1531 unsigned Reg = CSI[i].getReg();
1532
1533 // Only Darwin actually uses the VRSAVE register, but it can still appear
1534 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1535 // Darwin, ignore it.
1536 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1537 continue;
1538
1539 if (Reg == PPC::CR2) {
1540 CR2Spilled = true;
1541 // The spill slot is associated only with CR2, which is the
1542 // first nonvolatile spilled. Save it here.
1543 CSIIndex = i;
1544 continue;
1545 } else if (Reg == PPC::CR3) {
1546 CR3Spilled = true;
1547 continue;
1548 } else if (Reg == PPC::CR4) {
1549 CR4Spilled = true;
1550 continue;
1551 } else {
1552 // When we first encounter a non-CR register after seeing at
1553 // least one CR register, restore all spilled CRs together.
1554 if ((CR2Spilled || CR3Spilled || CR4Spilled)
1555 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1556 bool is31 = needsFP(*MF);
1557 restoreCRs(Subtarget.isPPC64(), is31,
1558 CR2Spilled, CR3Spilled, CR4Spilled,
1559 MBB, I, CSI, CSIIndex);
1560 CR2Spilled = CR3Spilled = CR4Spilled = false;
1561 }
1562
1563 // Default behavior for non-CR saves.
1564 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1565 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
1566 RC, TRI);
1567 assert(I != MBB.begin() &&
1568 "loadRegFromStackSlot didn't insert any code!");
1569 }
1570
1571 // Insert in reverse order.
1572 if (AtStart)
1573 I = MBB.begin();
1574 else {
1575 I = BeforeI;
1576 ++I;
1577 }
1578 }
1579
1580 // If we haven't yet spilled the CRs, do so now.
1581 if (CR2Spilled || CR3Spilled || CR4Spilled) {
1582 bool is31 = needsFP(*MF);
1583 restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
1584 MBB, I, CSI, CSIIndex);
1585 }
1586
1587 return true;
1588 }
1589