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Searched defs:UseIdx (Results 1 – 17 of 17) sorted by relevance

/external/llvm/lib/CodeGen/
DTargetSchedule.cpp145 unsigned UseIdx = 0; in findUseIdx() local
203 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx); in computeOperandLatency() local
DLiveRangeEdit.cpp119 SlotIndex UseIdx, in canRematerializeAt()
DRegisterCoalescer.cpp627 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI); in removeCopyByCommutingDef() local
679 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true); in removeCopyByCommutingDef() local
DInlineSpiller.cpp856 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true); in reMaterializeFor() local
DSplitKit.cpp432 SlotIndex UseIdx, in defFromParent()
DTwoAddressInstructionPass.cpp1480 SlotIndex UseIdx = MIIdx.getRegSlot(IsEarlyClobber); in processTiedPairs() local
DMachineVerifier.cpp1007 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI); in checkLiveness() local
DMachineInstr.cpp1177 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { in tieOperands()
/external/llvm/include/llvm/MC/
DMCInstrItineraries.h198 unsigned UseClass, unsigned UseIdx) const { in hasPipelineForwarding()
219 unsigned UseClass, unsigned UseIdx) const { in getOperandLatency()
DMCSubtargetInfo.h110 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, in getReadAdvanceCycles()
DMCSchedule.h87 unsigned UseIdx; member
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.h104 SDNode *UseNode, unsigned UseIdx) const override { in getOperandLatency()
DPPCInstrInfo.cpp1014 unsigned UseIdx; in FoldImmediate() local
/external/llvm/lib/Target/ARM/
DARMBaseInstrInfo.cpp3084 unsigned UseIdx, unsigned UseAlign) const { in getVSTMUseCycle()
3124 unsigned UseIdx, unsigned UseAlign) const { in getSTMUseCycle()
3154 unsigned UseIdx, unsigned UseAlign) const { in getOperandLatency()
3286 unsigned &UseIdx, unsigned &Dist) { in getBundledUseMI()
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp991 unsigned UseIdx = GroupIdx.back() + 1; in EmitSpecialNode() local
/external/llvm/include/llvm/Target/
DTargetInstrInfo.h884 const MachineInstr *UseMI, unsigned UseIdx) const { in hasHighOperandLatency()
/external/llvm/utils/TableGen/
DSubtargetEmitter.cpp992 for (unsigned UseIdx = 0, EndIdx = Reads.size(); in GenSchedClassTables() local