1 //=====-- AMDGPUSubtarget.h - Define Subtarget for the AMDIL ---*- C++ -*-====// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //==-----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief AMDGPU specific subclass of TargetSubtarget. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef AMDGPUSUBTARGET_H 16 #define AMDGPUSUBTARGET_H 17 #include "AMDGPU.h" 18 #include "AMDGPUInstrInfo.h" 19 #include "llvm/ADT/StringExtras.h" 20 #include "llvm/ADT/StringRef.h" 21 #include "llvm/Target/TargetSubtargetInfo.h" 22 23 #define GET_SUBTARGETINFO_HEADER 24 #include "AMDGPUGenSubtargetInfo.inc" 25 26 #define MAX_CB_SIZE (1 << 16) 27 28 namespace llvm { 29 30 class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo { 31 32 std::unique_ptr<AMDGPUInstrInfo> InstrInfo; 33 34 public: 35 enum Generation { 36 R600 = 0, 37 R700, 38 EVERGREEN, 39 NORTHERN_ISLANDS, 40 SOUTHERN_ISLANDS, 41 SEA_ISLANDS 42 }; 43 44 private: 45 std::string DevName; 46 bool Is64bit; 47 bool DumpCode; 48 bool R600ALUInst; 49 bool HasVertexCache; 50 short TexVTXClauseSize; 51 Generation Gen; 52 bool FP64; 53 bool CaymanISA; 54 bool EnableIRStructurizer; 55 bool EnableIfCvt; 56 unsigned WavefrontSize; 57 bool CFALUBug; 58 int LocalMemorySize; 59 60 InstrItineraryData InstrItins; 61 62 public: 63 AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS); 64 getInstrInfo()65 const AMDGPUInstrInfo *getInstrInfo() const { 66 return InstrInfo.get(); 67 } 68 getInstrItineraryData()69 const InstrItineraryData &getInstrItineraryData() const { 70 return InstrItins; 71 } 72 73 void ParseSubtargetFeatures(StringRef CPU, StringRef FS); 74 is64bit()75 bool is64bit() const { 76 return Is64bit; 77 } 78 hasVertexCache()79 bool hasVertexCache() const { 80 return HasVertexCache; 81 } 82 getTexVTXClauseSize()83 short getTexVTXClauseSize() const { 84 return TexVTXClauseSize; 85 } 86 getGeneration()87 Generation getGeneration() const { 88 return Gen; 89 } 90 hasHWFP64()91 bool hasHWFP64() const { 92 return FP64; 93 } 94 hasCaymanISA()95 bool hasCaymanISA() const { 96 return CaymanISA; 97 } 98 hasBFE()99 bool hasBFE() const { 100 return (getGeneration() >= EVERGREEN); 101 } 102 hasBFI()103 bool hasBFI() const { 104 return (getGeneration() >= EVERGREEN); 105 } 106 hasBFM()107 bool hasBFM() const { 108 return hasBFE(); 109 } 110 hasBCNT(unsigned Size)111 bool hasBCNT(unsigned Size) const { 112 if (Size == 32) 113 return (getGeneration() >= EVERGREEN); 114 115 assert(Size == 64); 116 return (getGeneration() >= SOUTHERN_ISLANDS); 117 } 118 hasMulU24()119 bool hasMulU24() const { 120 return (getGeneration() >= EVERGREEN); 121 } 122 hasMulI24()123 bool hasMulI24() const { 124 return (getGeneration() >= SOUTHERN_ISLANDS || 125 hasCaymanISA()); 126 } 127 IsIRStructurizerEnabled()128 bool IsIRStructurizerEnabled() const { 129 return EnableIRStructurizer; 130 } 131 isIfCvtEnabled()132 bool isIfCvtEnabled() const { 133 return EnableIfCvt; 134 } 135 getWavefrontSize()136 unsigned getWavefrontSize() const { 137 return WavefrontSize; 138 } 139 140 unsigned getStackEntrySize() const; 141 hasCFAluBug()142 bool hasCFAluBug() const { 143 assert(getGeneration() <= NORTHERN_ISLANDS); 144 return CFALUBug; 145 } 146 getLocalMemorySize()147 int getLocalMemorySize() const { 148 return LocalMemorySize; 149 } 150 enableMachineScheduler()151 bool enableMachineScheduler() const override { 152 return getGeneration() <= NORTHERN_ISLANDS; 153 } 154 155 // Helper functions to simplify if statements isTargetELF()156 bool isTargetELF() const { 157 return false; 158 } 159 getDeviceName()160 StringRef getDeviceName() const { 161 return DevName; 162 } 163 dumpCode()164 bool dumpCode() const { 165 return DumpCode; 166 } r600ALUEncoding()167 bool r600ALUEncoding() const { 168 return R600ALUInst; 169 } 170 }; 171 172 } // End namespace llvm 173 174 #endif // AMDGPUSUBTARGET_H 175