1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4
5 #ifndef V8_ARM64_CONSTANTS_ARM64_H_
6 #define V8_ARM64_CONSTANTS_ARM64_H_
7
8
9 // Assert that this is an LP64 system.
10 STATIC_ASSERT(sizeof(int) == sizeof(int32_t)); // NOLINT(runtime/sizeof)
11 STATIC_ASSERT(sizeof(long) == sizeof(int64_t)); // NOLINT(runtime/int)
12 STATIC_ASSERT(sizeof(void *) == sizeof(int64_t)); // NOLINT(runtime/sizeof)
13 STATIC_ASSERT(sizeof(1) == sizeof(int32_t)); // NOLINT(runtime/sizeof)
14 STATIC_ASSERT(sizeof(1L) == sizeof(int64_t)); // NOLINT(runtime/sizeof)
15
16
17 // Get the standard printf format macros for C99 stdint types.
18 #define __STDC_FORMAT_MACROS
19 #include <inttypes.h>
20
21
22 namespace v8 {
23 namespace internal {
24
25
26 const unsigned kInstructionSize = 4;
27 const unsigned kInstructionSizeLog2 = 2;
28 const unsigned kLoadLiteralScaleLog2 = 2;
29 const unsigned kMaxLoadLiteralRange = 1 * MB;
30
31 const unsigned kNumberOfRegisters = 32;
32 const unsigned kNumberOfFPRegisters = 32;
33 // Callee saved registers are x19-x30(lr).
34 const int kNumberOfCalleeSavedRegisters = 11;
35 const int kFirstCalleeSavedRegisterIndex = 19;
36 // Callee saved FP registers are d8-d15.
37 const int kNumberOfCalleeSavedFPRegisters = 8;
38 const int kFirstCalleeSavedFPRegisterIndex = 8;
39 // Callee saved registers with no specific purpose in JS are x19-x25.
40 const unsigned kJSCalleeSavedRegList = 0x03f80000;
41 // TODO(all): k<Y>RegSize should probably be k<Y>RegSizeInBits.
42 const unsigned kWRegSizeInBits = 32;
43 const unsigned kWRegSizeInBitsLog2 = 5;
44 const unsigned kWRegSize = kWRegSizeInBits >> 3;
45 const unsigned kWRegSizeLog2 = kWRegSizeInBitsLog2 - 3;
46 const unsigned kXRegSizeInBits = 64;
47 const unsigned kXRegSizeInBitsLog2 = 6;
48 const unsigned kXRegSize = kXRegSizeInBits >> 3;
49 const unsigned kXRegSizeLog2 = kXRegSizeInBitsLog2 - 3;
50 const unsigned kSRegSizeInBits = 32;
51 const unsigned kSRegSizeInBitsLog2 = 5;
52 const unsigned kSRegSize = kSRegSizeInBits >> 3;
53 const unsigned kSRegSizeLog2 = kSRegSizeInBitsLog2 - 3;
54 const unsigned kDRegSizeInBits = 64;
55 const unsigned kDRegSizeInBitsLog2 = 6;
56 const unsigned kDRegSize = kDRegSizeInBits >> 3;
57 const unsigned kDRegSizeLog2 = kDRegSizeInBitsLog2 - 3;
58 const int64_t kWRegMask = 0x00000000ffffffffL;
59 const int64_t kXRegMask = 0xffffffffffffffffL;
60 const int64_t kSRegMask = 0x00000000ffffffffL;
61 const int64_t kDRegMask = 0xffffffffffffffffL;
62 // TODO(all) check if the expression below works on all compilers or if it
63 // triggers an overflow error.
64 const int64_t kDSignBit = 63;
65 const int64_t kDSignMask = 0x1L << kDSignBit;
66 const int64_t kSSignBit = 31;
67 const int64_t kSSignMask = 0x1L << kSSignBit;
68 const int64_t kXSignBit = 63;
69 const int64_t kXSignMask = 0x1L << kXSignBit;
70 const int64_t kWSignBit = 31;
71 const int64_t kWSignMask = 0x1L << kWSignBit;
72 const int64_t kDQuietNanBit = 51;
73 const int64_t kDQuietNanMask = 0x1L << kDQuietNanBit;
74 const int64_t kSQuietNanBit = 22;
75 const int64_t kSQuietNanMask = 0x1L << kSQuietNanBit;
76 const int64_t kByteMask = 0xffL;
77 const int64_t kHalfWordMask = 0xffffL;
78 const int64_t kWordMask = 0xffffffffL;
79 const uint64_t kXMaxUInt = 0xffffffffffffffffUL;
80 const uint64_t kWMaxUInt = 0xffffffffUL;
81 const int64_t kXMaxInt = 0x7fffffffffffffffL;
82 const int64_t kXMinInt = 0x8000000000000000L;
83 const int32_t kWMaxInt = 0x7fffffff;
84 const int32_t kWMinInt = 0x80000000;
85 const unsigned kFramePointerRegCode = 29;
86 const unsigned kLinkRegCode = 30;
87 const unsigned kZeroRegCode = 31;
88 const unsigned kJSSPCode = 28;
89 const unsigned kSPRegInternalCode = 63;
90 const unsigned kRegCodeMask = 0x1f;
91 const unsigned kShiftAmountWRegMask = 0x1f;
92 const unsigned kShiftAmountXRegMask = 0x3f;
93 // Standard machine types defined by AAPCS64.
94 const unsigned kByteSize = 8;
95 const unsigned kByteSizeInBytes = kByteSize >> 3;
96 const unsigned kHalfWordSize = 16;
97 const unsigned kHalfWordSizeLog2 = 4;
98 const unsigned kHalfWordSizeInBytes = kHalfWordSize >> 3;
99 const unsigned kHalfWordSizeInBytesLog2 = kHalfWordSizeLog2 - 3;
100 const unsigned kWordSize = 32;
101 const unsigned kWordSizeLog2 = 5;
102 const unsigned kWordSizeInBytes = kWordSize >> 3;
103 const unsigned kWordSizeInBytesLog2 = kWordSizeLog2 - 3;
104 const unsigned kDoubleWordSize = 64;
105 const unsigned kDoubleWordSizeInBytes = kDoubleWordSize >> 3;
106 const unsigned kQuadWordSize = 128;
107 const unsigned kQuadWordSizeInBytes = kQuadWordSize >> 3;
108 // AArch64 floating-point specifics. These match IEEE-754.
109 const unsigned kDoubleMantissaBits = 52;
110 const unsigned kDoubleExponentBits = 11;
111 const unsigned kDoubleExponentBias = 1023;
112 const unsigned kFloatMantissaBits = 23;
113 const unsigned kFloatExponentBits = 8;
114
115 #define REGISTER_CODE_LIST(R) \
116 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \
117 R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) \
118 R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23) \
119 R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31)
120
121 #define INSTRUCTION_FIELDS_LIST(V_) \
122 /* Register fields */ \
123 V_(Rd, 4, 0, Bits) /* Destination register. */ \
124 V_(Rn, 9, 5, Bits) /* First source register. */ \
125 V_(Rm, 20, 16, Bits) /* Second source register. */ \
126 V_(Ra, 14, 10, Bits) /* Third source register. */ \
127 V_(Rt, 4, 0, Bits) /* Load dest / store source. */ \
128 V_(Rt2, 14, 10, Bits) /* Load second dest / */ \
129 /* store second source. */ \
130 V_(PrefetchMode, 4, 0, Bits) \
131 \
132 /* Common bits */ \
133 V_(SixtyFourBits, 31, 31, Bits) \
134 V_(FlagsUpdate, 29, 29, Bits) \
135 \
136 /* PC relative addressing */ \
137 V_(ImmPCRelHi, 23, 5, SignedBits) \
138 V_(ImmPCRelLo, 30, 29, Bits) \
139 \
140 /* Add/subtract/logical shift register */ \
141 V_(ShiftDP, 23, 22, Bits) \
142 V_(ImmDPShift, 15, 10, Bits) \
143 \
144 /* Add/subtract immediate */ \
145 V_(ImmAddSub, 21, 10, Bits) \
146 V_(ShiftAddSub, 23, 22, Bits) \
147 \
148 /* Add/substract extend */ \
149 V_(ImmExtendShift, 12, 10, Bits) \
150 V_(ExtendMode, 15, 13, Bits) \
151 \
152 /* Move wide */ \
153 V_(ImmMoveWide, 20, 5, Bits) \
154 V_(ShiftMoveWide, 22, 21, Bits) \
155 \
156 /* Logical immediate, bitfield and extract */ \
157 V_(BitN, 22, 22, Bits) \
158 V_(ImmRotate, 21, 16, Bits) \
159 V_(ImmSetBits, 15, 10, Bits) \
160 V_(ImmR, 21, 16, Bits) \
161 V_(ImmS, 15, 10, Bits) \
162 \
163 /* Test and branch immediate */ \
164 V_(ImmTestBranch, 18, 5, SignedBits) \
165 V_(ImmTestBranchBit40, 23, 19, Bits) \
166 V_(ImmTestBranchBit5, 31, 31, Bits) \
167 \
168 /* Conditionals */ \
169 V_(Condition, 15, 12, Bits) \
170 V_(ConditionBranch, 3, 0, Bits) \
171 V_(Nzcv, 3, 0, Bits) \
172 V_(ImmCondCmp, 20, 16, Bits) \
173 V_(ImmCondBranch, 23, 5, SignedBits) \
174 \
175 /* Floating point */ \
176 V_(FPType, 23, 22, Bits) \
177 V_(ImmFP, 20, 13, Bits) \
178 V_(FPScale, 15, 10, Bits) \
179 \
180 /* Load Store */ \
181 V_(ImmLS, 20, 12, SignedBits) \
182 V_(ImmLSUnsigned, 21, 10, Bits) \
183 V_(ImmLSPair, 21, 15, SignedBits) \
184 V_(SizeLS, 31, 30, Bits) \
185 V_(ImmShiftLS, 12, 12, Bits) \
186 \
187 /* Other immediates */ \
188 V_(ImmUncondBranch, 25, 0, SignedBits) \
189 V_(ImmCmpBranch, 23, 5, SignedBits) \
190 V_(ImmLLiteral, 23, 5, SignedBits) \
191 V_(ImmException, 20, 5, Bits) \
192 V_(ImmHint, 11, 5, Bits) \
193 V_(ImmBarrierDomain, 11, 10, Bits) \
194 V_(ImmBarrierType, 9, 8, Bits) \
195 \
196 /* System (MRS, MSR) */ \
197 V_(ImmSystemRegister, 19, 5, Bits) \
198 V_(SysO0, 19, 19, Bits) \
199 V_(SysOp1, 18, 16, Bits) \
200 V_(SysOp2, 7, 5, Bits) \
201 V_(CRn, 15, 12, Bits) \
202 V_(CRm, 11, 8, Bits) \
203
204
205 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \
206 /* NZCV */ \
207 V_(Flags, 31, 28, Bits, uint32_t) \
208 V_(N, 31, 31, Bits, bool) \
209 V_(Z, 30, 30, Bits, bool) \
210 V_(C, 29, 29, Bits, bool) \
211 V_(V, 28, 28, Bits, uint32_t) \
212 M_(NZCV, Flags_mask) \
213 \
214 /* FPCR */ \
215 V_(AHP, 26, 26, Bits, bool) \
216 V_(DN, 25, 25, Bits, bool) \
217 V_(FZ, 24, 24, Bits, bool) \
218 V_(RMode, 23, 22, Bits, FPRounding) \
219 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask)
220
221
222 // Fields offsets.
223 #define DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, unused_1, unused_2) \
224 const int Name##_offset = LowBit; \
225 const int Name##_width = HighBit - LowBit + 1; \
226 const uint32_t Name##_mask = ((1 << Name##_width) - 1) << LowBit;
227 #define DECLARE_INSTRUCTION_FIELDS_OFFSETS(Name, HighBit, LowBit, unused_1) \
228 DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, unused_1, unused_2)
229 #define NOTHING(A, B)
230 INSTRUCTION_FIELDS_LIST(DECLARE_INSTRUCTION_FIELDS_OFFSETS)
231 SYSTEM_REGISTER_FIELDS_LIST(DECLARE_FIELDS_OFFSETS, NOTHING)
232 #undef NOTHING
233 #undef DECLARE_FIELDS_OFFSETS
234 #undef DECLARE_INSTRUCTION_FIELDS_OFFSETS
235
236 // ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST), formed
237 // from ImmPCRelLo and ImmPCRelHi.
238 const int ImmPCRel_mask = ImmPCRelLo_mask | ImmPCRelHi_mask;
239
240 // Condition codes.
241 enum Condition {
242 eq = 0,
243 ne = 1,
244 hs = 2, cs = hs,
245 lo = 3, cc = lo,
246 mi = 4,
247 pl = 5,
248 vs = 6,
249 vc = 7,
250 hi = 8,
251 ls = 9,
252 ge = 10,
253 lt = 11,
254 gt = 12,
255 le = 13,
256 al = 14,
257 nv = 15 // Behaves as always/al.
258 };
259
NegateCondition(Condition cond)260 inline Condition NegateCondition(Condition cond) {
261 // Conditions al and nv behave identically, as "always true". They can't be
262 // inverted, because there is no never condition.
263 ASSERT((cond != al) && (cond != nv));
264 return static_cast<Condition>(cond ^ 1);
265 }
266
267 // Commute a condition such that {a cond b == b cond' a}.
CommuteCondition(Condition cond)268 inline Condition CommuteCondition(Condition cond) {
269 switch (cond) {
270 case lo:
271 return hi;
272 case hi:
273 return lo;
274 case hs:
275 return ls;
276 case ls:
277 return hs;
278 case lt:
279 return gt;
280 case gt:
281 return lt;
282 case ge:
283 return le;
284 case le:
285 return ge;
286 case eq:
287 return eq;
288 default:
289 // In practice this function is only used with a condition coming from
290 // TokenToCondition in lithium-codegen-arm64.cc. Any other condition is
291 // invalid as it doesn't necessary make sense to reverse it (consider
292 // 'mi' for instance).
293 UNREACHABLE();
294 return nv;
295 }
296 }
297
298 enum FlagsUpdate {
299 SetFlags = 1,
300 LeaveFlags = 0
301 };
302
303 enum StatusFlags {
304 NoFlag = 0,
305
306 // Derive the flag combinations from the system register bit descriptions.
307 NFlag = N_mask,
308 ZFlag = Z_mask,
309 CFlag = C_mask,
310 VFlag = V_mask,
311 NZFlag = NFlag | ZFlag,
312 NCFlag = NFlag | CFlag,
313 NVFlag = NFlag | VFlag,
314 ZCFlag = ZFlag | CFlag,
315 ZVFlag = ZFlag | VFlag,
316 CVFlag = CFlag | VFlag,
317 NZCFlag = NFlag | ZFlag | CFlag,
318 NZVFlag = NFlag | ZFlag | VFlag,
319 NCVFlag = NFlag | CFlag | VFlag,
320 ZCVFlag = ZFlag | CFlag | VFlag,
321 NZCVFlag = NFlag | ZFlag | CFlag | VFlag,
322
323 // Floating-point comparison results.
324 FPEqualFlag = ZCFlag,
325 FPLessThanFlag = NFlag,
326 FPGreaterThanFlag = CFlag,
327 FPUnorderedFlag = CVFlag
328 };
329
330 enum Shift {
331 NO_SHIFT = -1,
332 LSL = 0x0,
333 LSR = 0x1,
334 ASR = 0x2,
335 ROR = 0x3
336 };
337
338 enum Extend {
339 NO_EXTEND = -1,
340 UXTB = 0,
341 UXTH = 1,
342 UXTW = 2,
343 UXTX = 3,
344 SXTB = 4,
345 SXTH = 5,
346 SXTW = 6,
347 SXTX = 7
348 };
349
350 enum SystemHint {
351 NOP = 0,
352 YIELD = 1,
353 WFE = 2,
354 WFI = 3,
355 SEV = 4,
356 SEVL = 5
357 };
358
359 enum BarrierDomain {
360 OuterShareable = 0,
361 NonShareable = 1,
362 InnerShareable = 2,
363 FullSystem = 3
364 };
365
366 enum BarrierType {
367 BarrierOther = 0,
368 BarrierReads = 1,
369 BarrierWrites = 2,
370 BarrierAll = 3
371 };
372
373 // System/special register names.
374 // This information is not encoded as one field but as the concatenation of
375 // multiple fields (Op0<0>, Op1, Crn, Crm, Op2).
376 enum SystemRegister {
377 NZCV = ((0x1 << SysO0_offset) |
378 (0x3 << SysOp1_offset) |
379 (0x4 << CRn_offset) |
380 (0x2 << CRm_offset) |
381 (0x0 << SysOp2_offset)) >> ImmSystemRegister_offset,
382 FPCR = ((0x1 << SysO0_offset) |
383 (0x3 << SysOp1_offset) |
384 (0x4 << CRn_offset) |
385 (0x4 << CRm_offset) |
386 (0x0 << SysOp2_offset)) >> ImmSystemRegister_offset
387 };
388
389 // Instruction enumerations.
390 //
391 // These are the masks that define a class of instructions, and the list of
392 // instructions within each class. Each enumeration has a Fixed, FMask and
393 // Mask value.
394 //
395 // Fixed: The fixed bits in this instruction class.
396 // FMask: The mask used to extract the fixed bits in the class.
397 // Mask: The mask used to identify the instructions within a class.
398 //
399 // The enumerations can be used like this:
400 //
401 // ASSERT(instr->Mask(PCRelAddressingFMask) == PCRelAddressingFixed);
402 // switch(instr->Mask(PCRelAddressingMask)) {
403 // case ADR: Format("adr 'Xd, 'AddrPCRelByte"); break;
404 // case ADRP: Format("adrp 'Xd, 'AddrPCRelPage"); break;
405 // default: printf("Unknown instruction\n");
406 // }
407
408
409 // Generic fields.
410 enum GenericInstrField {
411 SixtyFourBits = 0x80000000,
412 ThirtyTwoBits = 0x00000000,
413 FP32 = 0x00000000,
414 FP64 = 0x00400000
415 };
416
417 // PC relative addressing.
418 enum PCRelAddressingOp {
419 PCRelAddressingFixed = 0x10000000,
420 PCRelAddressingFMask = 0x1F000000,
421 PCRelAddressingMask = 0x9F000000,
422 ADR = PCRelAddressingFixed | 0x00000000,
423 ADRP = PCRelAddressingFixed | 0x80000000
424 };
425
426 // Add/sub (immediate, shifted and extended.)
427 const int kSFOffset = 31;
428 enum AddSubOp {
429 AddSubOpMask = 0x60000000,
430 AddSubSetFlagsBit = 0x20000000,
431 ADD = 0x00000000,
432 ADDS = ADD | AddSubSetFlagsBit,
433 SUB = 0x40000000,
434 SUBS = SUB | AddSubSetFlagsBit
435 };
436
437 #define ADD_SUB_OP_LIST(V) \
438 V(ADD), \
439 V(ADDS), \
440 V(SUB), \
441 V(SUBS)
442
443 enum AddSubImmediateOp {
444 AddSubImmediateFixed = 0x11000000,
445 AddSubImmediateFMask = 0x1F000000,
446 AddSubImmediateMask = 0xFF000000,
447 #define ADD_SUB_IMMEDIATE(A) \
448 A##_w_imm = AddSubImmediateFixed | A, \
449 A##_x_imm = AddSubImmediateFixed | A | SixtyFourBits
450 ADD_SUB_OP_LIST(ADD_SUB_IMMEDIATE)
451 #undef ADD_SUB_IMMEDIATE
452 };
453
454 enum AddSubShiftedOp {
455 AddSubShiftedFixed = 0x0B000000,
456 AddSubShiftedFMask = 0x1F200000,
457 AddSubShiftedMask = 0xFF200000,
458 #define ADD_SUB_SHIFTED(A) \
459 A##_w_shift = AddSubShiftedFixed | A, \
460 A##_x_shift = AddSubShiftedFixed | A | SixtyFourBits
461 ADD_SUB_OP_LIST(ADD_SUB_SHIFTED)
462 #undef ADD_SUB_SHIFTED
463 };
464
465 enum AddSubExtendedOp {
466 AddSubExtendedFixed = 0x0B200000,
467 AddSubExtendedFMask = 0x1F200000,
468 AddSubExtendedMask = 0xFFE00000,
469 #define ADD_SUB_EXTENDED(A) \
470 A##_w_ext = AddSubExtendedFixed | A, \
471 A##_x_ext = AddSubExtendedFixed | A | SixtyFourBits
472 ADD_SUB_OP_LIST(ADD_SUB_EXTENDED)
473 #undef ADD_SUB_EXTENDED
474 };
475
476 // Add/sub with carry.
477 enum AddSubWithCarryOp {
478 AddSubWithCarryFixed = 0x1A000000,
479 AddSubWithCarryFMask = 0x1FE00000,
480 AddSubWithCarryMask = 0xFFE0FC00,
481 ADC_w = AddSubWithCarryFixed | ADD,
482 ADC_x = AddSubWithCarryFixed | ADD | SixtyFourBits,
483 ADC = ADC_w,
484 ADCS_w = AddSubWithCarryFixed | ADDS,
485 ADCS_x = AddSubWithCarryFixed | ADDS | SixtyFourBits,
486 SBC_w = AddSubWithCarryFixed | SUB,
487 SBC_x = AddSubWithCarryFixed | SUB | SixtyFourBits,
488 SBC = SBC_w,
489 SBCS_w = AddSubWithCarryFixed | SUBS,
490 SBCS_x = AddSubWithCarryFixed | SUBS | SixtyFourBits
491 };
492
493
494 // Logical (immediate and shifted register).
495 enum LogicalOp {
496 LogicalOpMask = 0x60200000,
497 NOT = 0x00200000,
498 AND = 0x00000000,
499 BIC = AND | NOT,
500 ORR = 0x20000000,
501 ORN = ORR | NOT,
502 EOR = 0x40000000,
503 EON = EOR | NOT,
504 ANDS = 0x60000000,
505 BICS = ANDS | NOT
506 };
507
508 // Logical immediate.
509 enum LogicalImmediateOp {
510 LogicalImmediateFixed = 0x12000000,
511 LogicalImmediateFMask = 0x1F800000,
512 LogicalImmediateMask = 0xFF800000,
513 AND_w_imm = LogicalImmediateFixed | AND,
514 AND_x_imm = LogicalImmediateFixed | AND | SixtyFourBits,
515 ORR_w_imm = LogicalImmediateFixed | ORR,
516 ORR_x_imm = LogicalImmediateFixed | ORR | SixtyFourBits,
517 EOR_w_imm = LogicalImmediateFixed | EOR,
518 EOR_x_imm = LogicalImmediateFixed | EOR | SixtyFourBits,
519 ANDS_w_imm = LogicalImmediateFixed | ANDS,
520 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits
521 };
522
523 // Logical shifted register.
524 enum LogicalShiftedOp {
525 LogicalShiftedFixed = 0x0A000000,
526 LogicalShiftedFMask = 0x1F000000,
527 LogicalShiftedMask = 0xFF200000,
528 AND_w = LogicalShiftedFixed | AND,
529 AND_x = LogicalShiftedFixed | AND | SixtyFourBits,
530 AND_shift = AND_w,
531 BIC_w = LogicalShiftedFixed | BIC,
532 BIC_x = LogicalShiftedFixed | BIC | SixtyFourBits,
533 BIC_shift = BIC_w,
534 ORR_w = LogicalShiftedFixed | ORR,
535 ORR_x = LogicalShiftedFixed | ORR | SixtyFourBits,
536 ORR_shift = ORR_w,
537 ORN_w = LogicalShiftedFixed | ORN,
538 ORN_x = LogicalShiftedFixed | ORN | SixtyFourBits,
539 ORN_shift = ORN_w,
540 EOR_w = LogicalShiftedFixed | EOR,
541 EOR_x = LogicalShiftedFixed | EOR | SixtyFourBits,
542 EOR_shift = EOR_w,
543 EON_w = LogicalShiftedFixed | EON,
544 EON_x = LogicalShiftedFixed | EON | SixtyFourBits,
545 EON_shift = EON_w,
546 ANDS_w = LogicalShiftedFixed | ANDS,
547 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits,
548 ANDS_shift = ANDS_w,
549 BICS_w = LogicalShiftedFixed | BICS,
550 BICS_x = LogicalShiftedFixed | BICS | SixtyFourBits,
551 BICS_shift = BICS_w
552 };
553
554 // Move wide immediate.
555 enum MoveWideImmediateOp {
556 MoveWideImmediateFixed = 0x12800000,
557 MoveWideImmediateFMask = 0x1F800000,
558 MoveWideImmediateMask = 0xFF800000,
559 MOVN = 0x00000000,
560 MOVZ = 0x40000000,
561 MOVK = 0x60000000,
562 MOVN_w = MoveWideImmediateFixed | MOVN,
563 MOVN_x = MoveWideImmediateFixed | MOVN | SixtyFourBits,
564 MOVZ_w = MoveWideImmediateFixed | MOVZ,
565 MOVZ_x = MoveWideImmediateFixed | MOVZ | SixtyFourBits,
566 MOVK_w = MoveWideImmediateFixed | MOVK,
567 MOVK_x = MoveWideImmediateFixed | MOVK | SixtyFourBits
568 };
569
570 // Bitfield.
571 const int kBitfieldNOffset = 22;
572 enum BitfieldOp {
573 BitfieldFixed = 0x13000000,
574 BitfieldFMask = 0x1F800000,
575 BitfieldMask = 0xFF800000,
576 SBFM_w = BitfieldFixed | 0x00000000,
577 SBFM_x = BitfieldFixed | 0x80000000,
578 SBFM = SBFM_w,
579 BFM_w = BitfieldFixed | 0x20000000,
580 BFM_x = BitfieldFixed | 0xA0000000,
581 BFM = BFM_w,
582 UBFM_w = BitfieldFixed | 0x40000000,
583 UBFM_x = BitfieldFixed | 0xC0000000,
584 UBFM = UBFM_w
585 // Bitfield N field.
586 };
587
588 // Extract.
589 enum ExtractOp {
590 ExtractFixed = 0x13800000,
591 ExtractFMask = 0x1F800000,
592 ExtractMask = 0xFFA00000,
593 EXTR_w = ExtractFixed | 0x00000000,
594 EXTR_x = ExtractFixed | 0x80000000,
595 EXTR = EXTR_w
596 };
597
598 // Unconditional branch.
599 enum UnconditionalBranchOp {
600 UnconditionalBranchFixed = 0x14000000,
601 UnconditionalBranchFMask = 0x7C000000,
602 UnconditionalBranchMask = 0xFC000000,
603 B = UnconditionalBranchFixed | 0x00000000,
604 BL = UnconditionalBranchFixed | 0x80000000
605 };
606
607 // Unconditional branch to register.
608 enum UnconditionalBranchToRegisterOp {
609 UnconditionalBranchToRegisterFixed = 0xD6000000,
610 UnconditionalBranchToRegisterFMask = 0xFE000000,
611 UnconditionalBranchToRegisterMask = 0xFFFFFC1F,
612 BR = UnconditionalBranchToRegisterFixed | 0x001F0000,
613 BLR = UnconditionalBranchToRegisterFixed | 0x003F0000,
614 RET = UnconditionalBranchToRegisterFixed | 0x005F0000
615 };
616
617 // Compare and branch.
618 enum CompareBranchOp {
619 CompareBranchFixed = 0x34000000,
620 CompareBranchFMask = 0x7E000000,
621 CompareBranchMask = 0xFF000000,
622 CBZ_w = CompareBranchFixed | 0x00000000,
623 CBZ_x = CompareBranchFixed | 0x80000000,
624 CBZ = CBZ_w,
625 CBNZ_w = CompareBranchFixed | 0x01000000,
626 CBNZ_x = CompareBranchFixed | 0x81000000,
627 CBNZ = CBNZ_w
628 };
629
630 // Test and branch.
631 enum TestBranchOp {
632 TestBranchFixed = 0x36000000,
633 TestBranchFMask = 0x7E000000,
634 TestBranchMask = 0x7F000000,
635 TBZ = TestBranchFixed | 0x00000000,
636 TBNZ = TestBranchFixed | 0x01000000
637 };
638
639 // Conditional branch.
640 enum ConditionalBranchOp {
641 ConditionalBranchFixed = 0x54000000,
642 ConditionalBranchFMask = 0xFE000000,
643 ConditionalBranchMask = 0xFF000010,
644 B_cond = ConditionalBranchFixed | 0x00000000
645 };
646
647 // System.
648 // System instruction encoding is complicated because some instructions use op
649 // and CR fields to encode parameters. To handle this cleanly, the system
650 // instructions are split into more than one enum.
651
652 enum SystemOp {
653 SystemFixed = 0xD5000000,
654 SystemFMask = 0xFFC00000
655 };
656
657 enum SystemSysRegOp {
658 SystemSysRegFixed = 0xD5100000,
659 SystemSysRegFMask = 0xFFD00000,
660 SystemSysRegMask = 0xFFF00000,
661 MRS = SystemSysRegFixed | 0x00200000,
662 MSR = SystemSysRegFixed | 0x00000000
663 };
664
665 enum SystemHintOp {
666 SystemHintFixed = 0xD503201F,
667 SystemHintFMask = 0xFFFFF01F,
668 SystemHintMask = 0xFFFFF01F,
669 HINT = SystemHintFixed | 0x00000000
670 };
671
672 // Exception.
673 enum ExceptionOp {
674 ExceptionFixed = 0xD4000000,
675 ExceptionFMask = 0xFF000000,
676 ExceptionMask = 0xFFE0001F,
677 HLT = ExceptionFixed | 0x00400000,
678 BRK = ExceptionFixed | 0x00200000,
679 SVC = ExceptionFixed | 0x00000001,
680 HVC = ExceptionFixed | 0x00000002,
681 SMC = ExceptionFixed | 0x00000003,
682 DCPS1 = ExceptionFixed | 0x00A00001,
683 DCPS2 = ExceptionFixed | 0x00A00002,
684 DCPS3 = ExceptionFixed | 0x00A00003
685 };
686 // Code used to spot hlt instructions that should not be hit.
687 const int kHltBadCode = 0xbad;
688
689 enum MemBarrierOp {
690 MemBarrierFixed = 0xD503309F,
691 MemBarrierFMask = 0xFFFFF09F,
692 MemBarrierMask = 0xFFFFF0FF,
693 DSB = MemBarrierFixed | 0x00000000,
694 DMB = MemBarrierFixed | 0x00000020,
695 ISB = MemBarrierFixed | 0x00000040
696 };
697
698 // Any load or store (including pair).
699 enum LoadStoreAnyOp {
700 LoadStoreAnyFMask = 0x0a000000,
701 LoadStoreAnyFixed = 0x08000000
702 };
703
704 // Any load pair or store pair.
705 enum LoadStorePairAnyOp {
706 LoadStorePairAnyFMask = 0x3a000000,
707 LoadStorePairAnyFixed = 0x28000000
708 };
709
710 #define LOAD_STORE_PAIR_OP_LIST(V) \
711 V(STP, w, 0x00000000), \
712 V(LDP, w, 0x00400000), \
713 V(LDPSW, x, 0x40400000), \
714 V(STP, x, 0x80000000), \
715 V(LDP, x, 0x80400000), \
716 V(STP, s, 0x04000000), \
717 V(LDP, s, 0x04400000), \
718 V(STP, d, 0x44000000), \
719 V(LDP, d, 0x44400000)
720
721 // Load/store pair (post, pre and offset.)
722 enum LoadStorePairOp {
723 LoadStorePairMask = 0xC4400000,
724 LoadStorePairLBit = 1 << 22,
725 #define LOAD_STORE_PAIR(A, B, C) \
726 A##_##B = C
727 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR)
728 #undef LOAD_STORE_PAIR
729 };
730
731 enum LoadStorePairPostIndexOp {
732 LoadStorePairPostIndexFixed = 0x28800000,
733 LoadStorePairPostIndexFMask = 0x3B800000,
734 LoadStorePairPostIndexMask = 0xFFC00000,
735 #define LOAD_STORE_PAIR_POST_INDEX(A, B, C) \
736 A##_##B##_post = LoadStorePairPostIndexFixed | A##_##B
737 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_POST_INDEX)
738 #undef LOAD_STORE_PAIR_POST_INDEX
739 };
740
741 enum LoadStorePairPreIndexOp {
742 LoadStorePairPreIndexFixed = 0x29800000,
743 LoadStorePairPreIndexFMask = 0x3B800000,
744 LoadStorePairPreIndexMask = 0xFFC00000,
745 #define LOAD_STORE_PAIR_PRE_INDEX(A, B, C) \
746 A##_##B##_pre = LoadStorePairPreIndexFixed | A##_##B
747 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_PRE_INDEX)
748 #undef LOAD_STORE_PAIR_PRE_INDEX
749 };
750
751 enum LoadStorePairOffsetOp {
752 LoadStorePairOffsetFixed = 0x29000000,
753 LoadStorePairOffsetFMask = 0x3B800000,
754 LoadStorePairOffsetMask = 0xFFC00000,
755 #define LOAD_STORE_PAIR_OFFSET(A, B, C) \
756 A##_##B##_off = LoadStorePairOffsetFixed | A##_##B
757 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_OFFSET)
758 #undef LOAD_STORE_PAIR_OFFSET
759 };
760
761 enum LoadStorePairNonTemporalOp {
762 LoadStorePairNonTemporalFixed = 0x28000000,
763 LoadStorePairNonTemporalFMask = 0x3B800000,
764 LoadStorePairNonTemporalMask = 0xFFC00000,
765 STNP_w = LoadStorePairNonTemporalFixed | STP_w,
766 LDNP_w = LoadStorePairNonTemporalFixed | LDP_w,
767 STNP_x = LoadStorePairNonTemporalFixed | STP_x,
768 LDNP_x = LoadStorePairNonTemporalFixed | LDP_x,
769 STNP_s = LoadStorePairNonTemporalFixed | STP_s,
770 LDNP_s = LoadStorePairNonTemporalFixed | LDP_s,
771 STNP_d = LoadStorePairNonTemporalFixed | STP_d,
772 LDNP_d = LoadStorePairNonTemporalFixed | LDP_d
773 };
774
775 // Load literal.
776 enum LoadLiteralOp {
777 LoadLiteralFixed = 0x18000000,
778 LoadLiteralFMask = 0x3B000000,
779 LoadLiteralMask = 0xFF000000,
780 LDR_w_lit = LoadLiteralFixed | 0x00000000,
781 LDR_x_lit = LoadLiteralFixed | 0x40000000,
782 LDRSW_x_lit = LoadLiteralFixed | 0x80000000,
783 PRFM_lit = LoadLiteralFixed | 0xC0000000,
784 LDR_s_lit = LoadLiteralFixed | 0x04000000,
785 LDR_d_lit = LoadLiteralFixed | 0x44000000
786 };
787
788 #define LOAD_STORE_OP_LIST(V) \
789 V(ST, RB, w, 0x00000000), \
790 V(ST, RH, w, 0x40000000), \
791 V(ST, R, w, 0x80000000), \
792 V(ST, R, x, 0xC0000000), \
793 V(LD, RB, w, 0x00400000), \
794 V(LD, RH, w, 0x40400000), \
795 V(LD, R, w, 0x80400000), \
796 V(LD, R, x, 0xC0400000), \
797 V(LD, RSB, x, 0x00800000), \
798 V(LD, RSH, x, 0x40800000), \
799 V(LD, RSW, x, 0x80800000), \
800 V(LD, RSB, w, 0x00C00000), \
801 V(LD, RSH, w, 0x40C00000), \
802 V(ST, R, s, 0x84000000), \
803 V(ST, R, d, 0xC4000000), \
804 V(LD, R, s, 0x84400000), \
805 V(LD, R, d, 0xC4400000)
806
807
808 // Load/store unscaled offset.
809 enum LoadStoreUnscaledOffsetOp {
810 LoadStoreUnscaledOffsetFixed = 0x38000000,
811 LoadStoreUnscaledOffsetFMask = 0x3B200C00,
812 LoadStoreUnscaledOffsetMask = 0xFFE00C00,
813 #define LOAD_STORE_UNSCALED(A, B, C, D) \
814 A##U##B##_##C = LoadStoreUnscaledOffsetFixed | D
815 LOAD_STORE_OP_LIST(LOAD_STORE_UNSCALED)
816 #undef LOAD_STORE_UNSCALED
817 };
818
819 // Load/store (post, pre, offset and unsigned.)
820 enum LoadStoreOp {
821 LoadStoreOpMask = 0xC4C00000,
822 #define LOAD_STORE(A, B, C, D) \
823 A##B##_##C = D
824 LOAD_STORE_OP_LIST(LOAD_STORE),
825 #undef LOAD_STORE
826 PRFM = 0xC0800000
827 };
828
829 // Load/store post index.
830 enum LoadStorePostIndex {
831 LoadStorePostIndexFixed = 0x38000400,
832 LoadStorePostIndexFMask = 0x3B200C00,
833 LoadStorePostIndexMask = 0xFFE00C00,
834 #define LOAD_STORE_POST_INDEX(A, B, C, D) \
835 A##B##_##C##_post = LoadStorePostIndexFixed | D
836 LOAD_STORE_OP_LIST(LOAD_STORE_POST_INDEX)
837 #undef LOAD_STORE_POST_INDEX
838 };
839
840 // Load/store pre index.
841 enum LoadStorePreIndex {
842 LoadStorePreIndexFixed = 0x38000C00,
843 LoadStorePreIndexFMask = 0x3B200C00,
844 LoadStorePreIndexMask = 0xFFE00C00,
845 #define LOAD_STORE_PRE_INDEX(A, B, C, D) \
846 A##B##_##C##_pre = LoadStorePreIndexFixed | D
847 LOAD_STORE_OP_LIST(LOAD_STORE_PRE_INDEX)
848 #undef LOAD_STORE_PRE_INDEX
849 };
850
851 // Load/store unsigned offset.
852 enum LoadStoreUnsignedOffset {
853 LoadStoreUnsignedOffsetFixed = 0x39000000,
854 LoadStoreUnsignedOffsetFMask = 0x3B000000,
855 LoadStoreUnsignedOffsetMask = 0xFFC00000,
856 PRFM_unsigned = LoadStoreUnsignedOffsetFixed | PRFM,
857 #define LOAD_STORE_UNSIGNED_OFFSET(A, B, C, D) \
858 A##B##_##C##_unsigned = LoadStoreUnsignedOffsetFixed | D
859 LOAD_STORE_OP_LIST(LOAD_STORE_UNSIGNED_OFFSET)
860 #undef LOAD_STORE_UNSIGNED_OFFSET
861 };
862
863 // Load/store register offset.
864 enum LoadStoreRegisterOffset {
865 LoadStoreRegisterOffsetFixed = 0x38200800,
866 LoadStoreRegisterOffsetFMask = 0x3B200C00,
867 LoadStoreRegisterOffsetMask = 0xFFE00C00,
868 PRFM_reg = LoadStoreRegisterOffsetFixed | PRFM,
869 #define LOAD_STORE_REGISTER_OFFSET(A, B, C, D) \
870 A##B##_##C##_reg = LoadStoreRegisterOffsetFixed | D
871 LOAD_STORE_OP_LIST(LOAD_STORE_REGISTER_OFFSET)
872 #undef LOAD_STORE_REGISTER_OFFSET
873 };
874
875 // Conditional compare.
876 enum ConditionalCompareOp {
877 ConditionalCompareMask = 0x60000000,
878 CCMN = 0x20000000,
879 CCMP = 0x60000000
880 };
881
882 // Conditional compare register.
883 enum ConditionalCompareRegisterOp {
884 ConditionalCompareRegisterFixed = 0x1A400000,
885 ConditionalCompareRegisterFMask = 0x1FE00800,
886 ConditionalCompareRegisterMask = 0xFFE00C10,
887 CCMN_w = ConditionalCompareRegisterFixed | CCMN,
888 CCMN_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMN,
889 CCMP_w = ConditionalCompareRegisterFixed | CCMP,
890 CCMP_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMP
891 };
892
893 // Conditional compare immediate.
894 enum ConditionalCompareImmediateOp {
895 ConditionalCompareImmediateFixed = 0x1A400800,
896 ConditionalCompareImmediateFMask = 0x1FE00800,
897 ConditionalCompareImmediateMask = 0xFFE00C10,
898 CCMN_w_imm = ConditionalCompareImmediateFixed | CCMN,
899 CCMN_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMN,
900 CCMP_w_imm = ConditionalCompareImmediateFixed | CCMP,
901 CCMP_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMP
902 };
903
904 // Conditional select.
905 enum ConditionalSelectOp {
906 ConditionalSelectFixed = 0x1A800000,
907 ConditionalSelectFMask = 0x1FE00000,
908 ConditionalSelectMask = 0xFFE00C00,
909 CSEL_w = ConditionalSelectFixed | 0x00000000,
910 CSEL_x = ConditionalSelectFixed | 0x80000000,
911 CSEL = CSEL_w,
912 CSINC_w = ConditionalSelectFixed | 0x00000400,
913 CSINC_x = ConditionalSelectFixed | 0x80000400,
914 CSINC = CSINC_w,
915 CSINV_w = ConditionalSelectFixed | 0x40000000,
916 CSINV_x = ConditionalSelectFixed | 0xC0000000,
917 CSINV = CSINV_w,
918 CSNEG_w = ConditionalSelectFixed | 0x40000400,
919 CSNEG_x = ConditionalSelectFixed | 0xC0000400,
920 CSNEG = CSNEG_w
921 };
922
923 // Data processing 1 source.
924 enum DataProcessing1SourceOp {
925 DataProcessing1SourceFixed = 0x5AC00000,
926 DataProcessing1SourceFMask = 0x5FE00000,
927 DataProcessing1SourceMask = 0xFFFFFC00,
928 RBIT = DataProcessing1SourceFixed | 0x00000000,
929 RBIT_w = RBIT,
930 RBIT_x = RBIT | SixtyFourBits,
931 REV16 = DataProcessing1SourceFixed | 0x00000400,
932 REV16_w = REV16,
933 REV16_x = REV16 | SixtyFourBits,
934 REV = DataProcessing1SourceFixed | 0x00000800,
935 REV_w = REV,
936 REV32_x = REV | SixtyFourBits,
937 REV_x = DataProcessing1SourceFixed | SixtyFourBits | 0x00000C00,
938 CLZ = DataProcessing1SourceFixed | 0x00001000,
939 CLZ_w = CLZ,
940 CLZ_x = CLZ | SixtyFourBits,
941 CLS = DataProcessing1SourceFixed | 0x00001400,
942 CLS_w = CLS,
943 CLS_x = CLS | SixtyFourBits
944 };
945
946 // Data processing 2 source.
947 enum DataProcessing2SourceOp {
948 DataProcessing2SourceFixed = 0x1AC00000,
949 DataProcessing2SourceFMask = 0x5FE00000,
950 DataProcessing2SourceMask = 0xFFE0FC00,
951 UDIV_w = DataProcessing2SourceFixed | 0x00000800,
952 UDIV_x = DataProcessing2SourceFixed | 0x80000800,
953 UDIV = UDIV_w,
954 SDIV_w = DataProcessing2SourceFixed | 0x00000C00,
955 SDIV_x = DataProcessing2SourceFixed | 0x80000C00,
956 SDIV = SDIV_w,
957 LSLV_w = DataProcessing2SourceFixed | 0x00002000,
958 LSLV_x = DataProcessing2SourceFixed | 0x80002000,
959 LSLV = LSLV_w,
960 LSRV_w = DataProcessing2SourceFixed | 0x00002400,
961 LSRV_x = DataProcessing2SourceFixed | 0x80002400,
962 LSRV = LSRV_w,
963 ASRV_w = DataProcessing2SourceFixed | 0x00002800,
964 ASRV_x = DataProcessing2SourceFixed | 0x80002800,
965 ASRV = ASRV_w,
966 RORV_w = DataProcessing2SourceFixed | 0x00002C00,
967 RORV_x = DataProcessing2SourceFixed | 0x80002C00,
968 RORV = RORV_w,
969 CRC32B = DataProcessing2SourceFixed | 0x00004000,
970 CRC32H = DataProcessing2SourceFixed | 0x00004400,
971 CRC32W = DataProcessing2SourceFixed | 0x00004800,
972 CRC32X = DataProcessing2SourceFixed | SixtyFourBits | 0x00004C00,
973 CRC32CB = DataProcessing2SourceFixed | 0x00005000,
974 CRC32CH = DataProcessing2SourceFixed | 0x00005400,
975 CRC32CW = DataProcessing2SourceFixed | 0x00005800,
976 CRC32CX = DataProcessing2SourceFixed | SixtyFourBits | 0x00005C00
977 };
978
979 // Data processing 3 source.
980 enum DataProcessing3SourceOp {
981 DataProcessing3SourceFixed = 0x1B000000,
982 DataProcessing3SourceFMask = 0x1F000000,
983 DataProcessing3SourceMask = 0xFFE08000,
984 MADD_w = DataProcessing3SourceFixed | 0x00000000,
985 MADD_x = DataProcessing3SourceFixed | 0x80000000,
986 MADD = MADD_w,
987 MSUB_w = DataProcessing3SourceFixed | 0x00008000,
988 MSUB_x = DataProcessing3SourceFixed | 0x80008000,
989 MSUB = MSUB_w,
990 SMADDL_x = DataProcessing3SourceFixed | 0x80200000,
991 SMSUBL_x = DataProcessing3SourceFixed | 0x80208000,
992 SMULH_x = DataProcessing3SourceFixed | 0x80400000,
993 UMADDL_x = DataProcessing3SourceFixed | 0x80A00000,
994 UMSUBL_x = DataProcessing3SourceFixed | 0x80A08000,
995 UMULH_x = DataProcessing3SourceFixed | 0x80C00000
996 };
997
998 // Floating point compare.
999 enum FPCompareOp {
1000 FPCompareFixed = 0x1E202000,
1001 FPCompareFMask = 0x5F203C00,
1002 FPCompareMask = 0xFFE0FC1F,
1003 FCMP_s = FPCompareFixed | 0x00000000,
1004 FCMP_d = FPCompareFixed | FP64 | 0x00000000,
1005 FCMP = FCMP_s,
1006 FCMP_s_zero = FPCompareFixed | 0x00000008,
1007 FCMP_d_zero = FPCompareFixed | FP64 | 0x00000008,
1008 FCMP_zero = FCMP_s_zero,
1009 FCMPE_s = FPCompareFixed | 0x00000010,
1010 FCMPE_d = FPCompareFixed | FP64 | 0x00000010,
1011 FCMPE_s_zero = FPCompareFixed | 0x00000018,
1012 FCMPE_d_zero = FPCompareFixed | FP64 | 0x00000018
1013 };
1014
1015 // Floating point conditional compare.
1016 enum FPConditionalCompareOp {
1017 FPConditionalCompareFixed = 0x1E200400,
1018 FPConditionalCompareFMask = 0x5F200C00,
1019 FPConditionalCompareMask = 0xFFE00C10,
1020 FCCMP_s = FPConditionalCompareFixed | 0x00000000,
1021 FCCMP_d = FPConditionalCompareFixed | FP64 | 0x00000000,
1022 FCCMP = FCCMP_s,
1023 FCCMPE_s = FPConditionalCompareFixed | 0x00000010,
1024 FCCMPE_d = FPConditionalCompareFixed | FP64 | 0x00000010,
1025 FCCMPE = FCCMPE_s
1026 };
1027
1028 // Floating point conditional select.
1029 enum FPConditionalSelectOp {
1030 FPConditionalSelectFixed = 0x1E200C00,
1031 FPConditionalSelectFMask = 0x5F200C00,
1032 FPConditionalSelectMask = 0xFFE00C00,
1033 FCSEL_s = FPConditionalSelectFixed | 0x00000000,
1034 FCSEL_d = FPConditionalSelectFixed | FP64 | 0x00000000,
1035 FCSEL = FCSEL_s
1036 };
1037
1038 // Floating point immediate.
1039 enum FPImmediateOp {
1040 FPImmediateFixed = 0x1E201000,
1041 FPImmediateFMask = 0x5F201C00,
1042 FPImmediateMask = 0xFFE01C00,
1043 FMOV_s_imm = FPImmediateFixed | 0x00000000,
1044 FMOV_d_imm = FPImmediateFixed | FP64 | 0x00000000
1045 };
1046
1047 // Floating point data processing 1 source.
1048 enum FPDataProcessing1SourceOp {
1049 FPDataProcessing1SourceFixed = 0x1E204000,
1050 FPDataProcessing1SourceFMask = 0x5F207C00,
1051 FPDataProcessing1SourceMask = 0xFFFFFC00,
1052 FMOV_s = FPDataProcessing1SourceFixed | 0x00000000,
1053 FMOV_d = FPDataProcessing1SourceFixed | FP64 | 0x00000000,
1054 FMOV = FMOV_s,
1055 FABS_s = FPDataProcessing1SourceFixed | 0x00008000,
1056 FABS_d = FPDataProcessing1SourceFixed | FP64 | 0x00008000,
1057 FABS = FABS_s,
1058 FNEG_s = FPDataProcessing1SourceFixed | 0x00010000,
1059 FNEG_d = FPDataProcessing1SourceFixed | FP64 | 0x00010000,
1060 FNEG = FNEG_s,
1061 FSQRT_s = FPDataProcessing1SourceFixed | 0x00018000,
1062 FSQRT_d = FPDataProcessing1SourceFixed | FP64 | 0x00018000,
1063 FSQRT = FSQRT_s,
1064 FCVT_ds = FPDataProcessing1SourceFixed | 0x00028000,
1065 FCVT_sd = FPDataProcessing1SourceFixed | FP64 | 0x00020000,
1066 FRINTN_s = FPDataProcessing1SourceFixed | 0x00040000,
1067 FRINTN_d = FPDataProcessing1SourceFixed | FP64 | 0x00040000,
1068 FRINTN = FRINTN_s,
1069 FRINTP_s = FPDataProcessing1SourceFixed | 0x00048000,
1070 FRINTP_d = FPDataProcessing1SourceFixed | FP64 | 0x00048000,
1071 FRINTP = FRINTP_s,
1072 FRINTM_s = FPDataProcessing1SourceFixed | 0x00050000,
1073 FRINTM_d = FPDataProcessing1SourceFixed | FP64 | 0x00050000,
1074 FRINTM = FRINTM_s,
1075 FRINTZ_s = FPDataProcessing1SourceFixed | 0x00058000,
1076 FRINTZ_d = FPDataProcessing1SourceFixed | FP64 | 0x00058000,
1077 FRINTZ = FRINTZ_s,
1078 FRINTA_s = FPDataProcessing1SourceFixed | 0x00060000,
1079 FRINTA_d = FPDataProcessing1SourceFixed | FP64 | 0x00060000,
1080 FRINTA = FRINTA_s,
1081 FRINTX_s = FPDataProcessing1SourceFixed | 0x00070000,
1082 FRINTX_d = FPDataProcessing1SourceFixed | FP64 | 0x00070000,
1083 FRINTX = FRINTX_s,
1084 FRINTI_s = FPDataProcessing1SourceFixed | 0x00078000,
1085 FRINTI_d = FPDataProcessing1SourceFixed | FP64 | 0x00078000,
1086 FRINTI = FRINTI_s
1087 };
1088
1089 // Floating point data processing 2 source.
1090 enum FPDataProcessing2SourceOp {
1091 FPDataProcessing2SourceFixed = 0x1E200800,
1092 FPDataProcessing2SourceFMask = 0x5F200C00,
1093 FPDataProcessing2SourceMask = 0xFFE0FC00,
1094 FMUL = FPDataProcessing2SourceFixed | 0x00000000,
1095 FMUL_s = FMUL,
1096 FMUL_d = FMUL | FP64,
1097 FDIV = FPDataProcessing2SourceFixed | 0x00001000,
1098 FDIV_s = FDIV,
1099 FDIV_d = FDIV | FP64,
1100 FADD = FPDataProcessing2SourceFixed | 0x00002000,
1101 FADD_s = FADD,
1102 FADD_d = FADD | FP64,
1103 FSUB = FPDataProcessing2SourceFixed | 0x00003000,
1104 FSUB_s = FSUB,
1105 FSUB_d = FSUB | FP64,
1106 FMAX = FPDataProcessing2SourceFixed | 0x00004000,
1107 FMAX_s = FMAX,
1108 FMAX_d = FMAX | FP64,
1109 FMIN = FPDataProcessing2SourceFixed | 0x00005000,
1110 FMIN_s = FMIN,
1111 FMIN_d = FMIN | FP64,
1112 FMAXNM = FPDataProcessing2SourceFixed | 0x00006000,
1113 FMAXNM_s = FMAXNM,
1114 FMAXNM_d = FMAXNM | FP64,
1115 FMINNM = FPDataProcessing2SourceFixed | 0x00007000,
1116 FMINNM_s = FMINNM,
1117 FMINNM_d = FMINNM | FP64,
1118 FNMUL = FPDataProcessing2SourceFixed | 0x00008000,
1119 FNMUL_s = FNMUL,
1120 FNMUL_d = FNMUL | FP64
1121 };
1122
1123 // Floating point data processing 3 source.
1124 enum FPDataProcessing3SourceOp {
1125 FPDataProcessing3SourceFixed = 0x1F000000,
1126 FPDataProcessing3SourceFMask = 0x5F000000,
1127 FPDataProcessing3SourceMask = 0xFFE08000,
1128 FMADD_s = FPDataProcessing3SourceFixed | 0x00000000,
1129 FMSUB_s = FPDataProcessing3SourceFixed | 0x00008000,
1130 FNMADD_s = FPDataProcessing3SourceFixed | 0x00200000,
1131 FNMSUB_s = FPDataProcessing3SourceFixed | 0x00208000,
1132 FMADD_d = FPDataProcessing3SourceFixed | 0x00400000,
1133 FMSUB_d = FPDataProcessing3SourceFixed | 0x00408000,
1134 FNMADD_d = FPDataProcessing3SourceFixed | 0x00600000,
1135 FNMSUB_d = FPDataProcessing3SourceFixed | 0x00608000
1136 };
1137
1138 // Conversion between floating point and integer.
1139 enum FPIntegerConvertOp {
1140 FPIntegerConvertFixed = 0x1E200000,
1141 FPIntegerConvertFMask = 0x5F20FC00,
1142 FPIntegerConvertMask = 0xFFFFFC00,
1143 FCVTNS = FPIntegerConvertFixed | 0x00000000,
1144 FCVTNS_ws = FCVTNS,
1145 FCVTNS_xs = FCVTNS | SixtyFourBits,
1146 FCVTNS_wd = FCVTNS | FP64,
1147 FCVTNS_xd = FCVTNS | SixtyFourBits | FP64,
1148 FCVTNU = FPIntegerConvertFixed | 0x00010000,
1149 FCVTNU_ws = FCVTNU,
1150 FCVTNU_xs = FCVTNU | SixtyFourBits,
1151 FCVTNU_wd = FCVTNU | FP64,
1152 FCVTNU_xd = FCVTNU | SixtyFourBits | FP64,
1153 FCVTPS = FPIntegerConvertFixed | 0x00080000,
1154 FCVTPS_ws = FCVTPS,
1155 FCVTPS_xs = FCVTPS | SixtyFourBits,
1156 FCVTPS_wd = FCVTPS | FP64,
1157 FCVTPS_xd = FCVTPS | SixtyFourBits | FP64,
1158 FCVTPU = FPIntegerConvertFixed | 0x00090000,
1159 FCVTPU_ws = FCVTPU,
1160 FCVTPU_xs = FCVTPU | SixtyFourBits,
1161 FCVTPU_wd = FCVTPU | FP64,
1162 FCVTPU_xd = FCVTPU | SixtyFourBits | FP64,
1163 FCVTMS = FPIntegerConvertFixed | 0x00100000,
1164 FCVTMS_ws = FCVTMS,
1165 FCVTMS_xs = FCVTMS | SixtyFourBits,
1166 FCVTMS_wd = FCVTMS | FP64,
1167 FCVTMS_xd = FCVTMS | SixtyFourBits | FP64,
1168 FCVTMU = FPIntegerConvertFixed | 0x00110000,
1169 FCVTMU_ws = FCVTMU,
1170 FCVTMU_xs = FCVTMU | SixtyFourBits,
1171 FCVTMU_wd = FCVTMU | FP64,
1172 FCVTMU_xd = FCVTMU | SixtyFourBits | FP64,
1173 FCVTZS = FPIntegerConvertFixed | 0x00180000,
1174 FCVTZS_ws = FCVTZS,
1175 FCVTZS_xs = FCVTZS | SixtyFourBits,
1176 FCVTZS_wd = FCVTZS | FP64,
1177 FCVTZS_xd = FCVTZS | SixtyFourBits | FP64,
1178 FCVTZU = FPIntegerConvertFixed | 0x00190000,
1179 FCVTZU_ws = FCVTZU,
1180 FCVTZU_xs = FCVTZU | SixtyFourBits,
1181 FCVTZU_wd = FCVTZU | FP64,
1182 FCVTZU_xd = FCVTZU | SixtyFourBits | FP64,
1183 SCVTF = FPIntegerConvertFixed | 0x00020000,
1184 SCVTF_sw = SCVTF,
1185 SCVTF_sx = SCVTF | SixtyFourBits,
1186 SCVTF_dw = SCVTF | FP64,
1187 SCVTF_dx = SCVTF | SixtyFourBits | FP64,
1188 UCVTF = FPIntegerConvertFixed | 0x00030000,
1189 UCVTF_sw = UCVTF,
1190 UCVTF_sx = UCVTF | SixtyFourBits,
1191 UCVTF_dw = UCVTF | FP64,
1192 UCVTF_dx = UCVTF | SixtyFourBits | FP64,
1193 FCVTAS = FPIntegerConvertFixed | 0x00040000,
1194 FCVTAS_ws = FCVTAS,
1195 FCVTAS_xs = FCVTAS | SixtyFourBits,
1196 FCVTAS_wd = FCVTAS | FP64,
1197 FCVTAS_xd = FCVTAS | SixtyFourBits | FP64,
1198 FCVTAU = FPIntegerConvertFixed | 0x00050000,
1199 FCVTAU_ws = FCVTAU,
1200 FCVTAU_xs = FCVTAU | SixtyFourBits,
1201 FCVTAU_wd = FCVTAU | FP64,
1202 FCVTAU_xd = FCVTAU | SixtyFourBits | FP64,
1203 FMOV_ws = FPIntegerConvertFixed | 0x00060000,
1204 FMOV_sw = FPIntegerConvertFixed | 0x00070000,
1205 FMOV_xd = FMOV_ws | SixtyFourBits | FP64,
1206 FMOV_dx = FMOV_sw | SixtyFourBits | FP64
1207 };
1208
1209 // Conversion between fixed point and floating point.
1210 enum FPFixedPointConvertOp {
1211 FPFixedPointConvertFixed = 0x1E000000,
1212 FPFixedPointConvertFMask = 0x5F200000,
1213 FPFixedPointConvertMask = 0xFFFF0000,
1214 FCVTZS_fixed = FPFixedPointConvertFixed | 0x00180000,
1215 FCVTZS_ws_fixed = FCVTZS_fixed,
1216 FCVTZS_xs_fixed = FCVTZS_fixed | SixtyFourBits,
1217 FCVTZS_wd_fixed = FCVTZS_fixed | FP64,
1218 FCVTZS_xd_fixed = FCVTZS_fixed | SixtyFourBits | FP64,
1219 FCVTZU_fixed = FPFixedPointConvertFixed | 0x00190000,
1220 FCVTZU_ws_fixed = FCVTZU_fixed,
1221 FCVTZU_xs_fixed = FCVTZU_fixed | SixtyFourBits,
1222 FCVTZU_wd_fixed = FCVTZU_fixed | FP64,
1223 FCVTZU_xd_fixed = FCVTZU_fixed | SixtyFourBits | FP64,
1224 SCVTF_fixed = FPFixedPointConvertFixed | 0x00020000,
1225 SCVTF_sw_fixed = SCVTF_fixed,
1226 SCVTF_sx_fixed = SCVTF_fixed | SixtyFourBits,
1227 SCVTF_dw_fixed = SCVTF_fixed | FP64,
1228 SCVTF_dx_fixed = SCVTF_fixed | SixtyFourBits | FP64,
1229 UCVTF_fixed = FPFixedPointConvertFixed | 0x00030000,
1230 UCVTF_sw_fixed = UCVTF_fixed,
1231 UCVTF_sx_fixed = UCVTF_fixed | SixtyFourBits,
1232 UCVTF_dw_fixed = UCVTF_fixed | FP64,
1233 UCVTF_dx_fixed = UCVTF_fixed | SixtyFourBits | FP64
1234 };
1235
1236 // Unimplemented and unallocated instructions. These are defined to make fixed
1237 // bit assertion easier.
1238 enum UnimplementedOp {
1239 UnimplementedFixed = 0x00000000,
1240 UnimplementedFMask = 0x00000000
1241 };
1242
1243 enum UnallocatedOp {
1244 UnallocatedFixed = 0x00000000,
1245 UnallocatedFMask = 0x00000000
1246 };
1247
1248 } } // namespace v8::internal
1249
1250 #endif // V8_ARM64_CONSTANTS_ARM64_H_
1251