1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9
10 #include "llvm/MC/MCDisassembler.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "llvm/MC/MCContext.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCFixedLenDisassembler.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/LEB128.h"
23 #include "llvm/Support/MemoryObject.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include <vector>
27
28 using namespace llvm;
29
30 #define DEBUG_TYPE "arm-disassembler"
31
32 typedef MCDisassembler::DecodeStatus DecodeStatus;
33
34 namespace {
35 // Handles the condition code status of instructions in IT blocks
36 class ITStatus
37 {
38 public:
39 // Returns the condition code for instruction in IT block
getITCC()40 unsigned getITCC() {
41 unsigned CC = ARMCC::AL;
42 if (instrInITBlock())
43 CC = ITStates.back();
44 return CC;
45 }
46
47 // Advances the IT block state to the next T or E
advanceITState()48 void advanceITState() {
49 ITStates.pop_back();
50 }
51
52 // Returns true if the current instruction is in an IT block
instrInITBlock()53 bool instrInITBlock() {
54 return !ITStates.empty();
55 }
56
57 // Returns true if current instruction is the last instruction in an IT block
instrLastInITBlock()58 bool instrLastInITBlock() {
59 return ITStates.size() == 1;
60 }
61
62 // Called when decoding an IT instruction. Sets the IT state for the following
63 // instructions that for the IT block. Firstcond and Mask correspond to the
64 // fields in the IT instruction encoding.
setITState(char Firstcond,char Mask)65 void setITState(char Firstcond, char Mask) {
66 // (3 - the number of trailing zeros) is the number of then / else.
67 unsigned CondBit0 = Firstcond & 1;
68 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
70 assert(NumTZ <= 3 && "Invalid IT mask!");
71 // push condition codes onto the stack the correct order for the pops
72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
73 bool T = ((Mask >> Pos) & 1) == CondBit0;
74 if (T)
75 ITStates.push_back(CCBits);
76 else
77 ITStates.push_back(CCBits ^ 1);
78 }
79 ITStates.push_back(CCBits);
80 }
81
82 private:
83 std::vector<unsigned char> ITStates;
84 };
85 }
86
87 namespace {
88 /// ARMDisassembler - ARM disassembler for all ARM platforms.
89 class ARMDisassembler : public MCDisassembler {
90 public:
91 /// Constructor - Initializes the disassembler.
92 ///
ARMDisassembler(const MCSubtargetInfo & STI,MCContext & Ctx)93 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
94 MCDisassembler(STI, Ctx) {
95 }
96
~ARMDisassembler()97 ~ARMDisassembler() {
98 }
99
100 /// getInstruction - See MCDisassembler.
101 DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
102 const MemoryObject ®ion, uint64_t address,
103 raw_ostream &vStream,
104 raw_ostream &cStream) const override;
105 };
106
107 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
108 class ThumbDisassembler : public MCDisassembler {
109 public:
110 /// Constructor - Initializes the disassembler.
111 ///
ThumbDisassembler(const MCSubtargetInfo & STI,MCContext & Ctx)112 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
113 MCDisassembler(STI, Ctx) {
114 }
115
~ThumbDisassembler()116 ~ThumbDisassembler() {
117 }
118
119 /// getInstruction - See MCDisassembler.
120 DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
121 const MemoryObject ®ion, uint64_t address,
122 raw_ostream &vStream,
123 raw_ostream &cStream) const override;
124
125 private:
126 mutable ITStatus ITBlock;
127 DecodeStatus AddThumbPredicate(MCInst&) const;
128 void UpdateThumbVFPPredicate(MCInst&) const;
129 };
130 }
131
Check(DecodeStatus & Out,DecodeStatus In)132 static bool Check(DecodeStatus &Out, DecodeStatus In) {
133 switch (In) {
134 case MCDisassembler::Success:
135 // Out stays the same.
136 return true;
137 case MCDisassembler::SoftFail:
138 Out = In;
139 return true;
140 case MCDisassembler::Fail:
141 Out = In;
142 return false;
143 }
144 llvm_unreachable("Invalid DecodeStatus!");
145 }
146
147
148 // Forward declare these because the autogenerated code will reference them.
149 // Definitions are further down.
150 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
151 uint64_t Address, const void *Decoder);
152 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
153 unsigned RegNo, uint64_t Address,
154 const void *Decoder);
155 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
156 unsigned RegNo, uint64_t Address,
157 const void *Decoder);
158 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
159 uint64_t Address, const void *Decoder);
160 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
161 uint64_t Address, const void *Decoder);
162 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
163 uint64_t Address, const void *Decoder);
164 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
165 uint64_t Address, const void *Decoder);
166 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
167 uint64_t Address, const void *Decoder);
168 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
169 uint64_t Address, const void *Decoder);
170 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
171 uint64_t Address, const void *Decoder);
172 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
173 unsigned RegNo,
174 uint64_t Address,
175 const void *Decoder);
176 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
177 uint64_t Address, const void *Decoder);
178 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
179 uint64_t Address, const void *Decoder);
180 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
181 unsigned RegNo, uint64_t Address,
182 const void *Decoder);
183
184 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
185 uint64_t Address, const void *Decoder);
186 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
187 uint64_t Address, const void *Decoder);
188 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
189 uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
191 uint64_t Address, const void *Decoder);
192 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
193 uint64_t Address, const void *Decoder);
194 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
195 uint64_t Address, const void *Decoder);
196
197 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
198 uint64_t Address, const void *Decoder);
199 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
200 uint64_t Address, const void *Decoder);
201 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
202 unsigned Insn,
203 uint64_t Address,
204 const void *Decoder);
205 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
206 uint64_t Address, const void *Decoder);
207 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
208 uint64_t Address, const void *Decoder);
209 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
210 uint64_t Address, const void *Decoder);
211 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
212 uint64_t Address, const void *Decoder);
213
214 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
215 unsigned Insn,
216 uint64_t Adddress,
217 const void *Decoder);
218 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
219 uint64_t Address, const void *Decoder);
220 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
221 uint64_t Address, const void *Decoder);
222 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
223 uint64_t Address, const void *Decoder);
224 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
225 uint64_t Address, const void *Decoder);
226 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
227 uint64_t Address, const void *Decoder);
228 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
229 uint64_t Address, const void *Decoder);
230 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
231 uint64_t Address, const void *Decoder);
232 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
233 uint64_t Address, const void *Decoder);
234 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
235 uint64_t Address, const void *Decoder);
236 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
237 uint64_t Address, const void *Decoder);
238 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
239 uint64_t Address, const void *Decoder);
240 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
241 uint64_t Address, const void *Decoder);
242 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
243 uint64_t Address, const void *Decoder);
244 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
245 uint64_t Address, const void *Decoder);
246 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
247 uint64_t Address, const void *Decoder);
248 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
249 uint64_t Address, const void *Decoder);
250 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
251 uint64_t Address, const void *Decoder);
252 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
253 uint64_t Address, const void *Decoder);
254 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
255 uint64_t Address, const void *Decoder);
256 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
257 uint64_t Address, const void *Decoder);
258 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
259 uint64_t Address, const void *Decoder);
260 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
261 uint64_t Address, const void *Decoder);
262 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
263 uint64_t Address, const void *Decoder);
264 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
265 uint64_t Address, const void *Decoder);
266 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
267 uint64_t Address, const void *Decoder);
268 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
269 uint64_t Address, const void *Decoder);
270 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
271 uint64_t Address, const void *Decoder);
272 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
273 uint64_t Address, const void *Decoder);
274 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
275 uint64_t Address, const void *Decoder);
276 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
277 uint64_t Address, const void *Decoder);
278 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
279 uint64_t Address, const void *Decoder);
280 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
281 uint64_t Address, const void *Decoder);
282 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
283 uint64_t Address, const void *Decoder);
284 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
285 uint64_t Address, const void *Decoder);
286 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
287 uint64_t Address, const void *Decoder);
288 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
289 uint64_t Address, const void *Decoder);
290 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
291 uint64_t Address, const void *Decoder);
292 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
293 uint64_t Address, const void *Decoder);
294 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
295 uint64_t Address, const void *Decoder);
296 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
297 uint64_t Address, const void *Decoder);
298 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
299 uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
301 uint64_t Address, const void *Decoder);
302 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
303 uint64_t Address, const void *Decoder);
304 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
305 uint64_t Address, const void *Decoder);
306 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
307 uint64_t Address, const void *Decoder);
308 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
309 uint64_t Address, const void *Decoder);
310 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
311 uint64_t Address, const void *Decoder);
312 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
313 uint64_t Address, const void *Decoder);
314 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
315 uint64_t Address, const void *Decoder);
316 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
317 uint64_t Address, const void *Decoder);
318 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
319 uint64_t Address, const void *Decoder);
320 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
321 uint64_t Address, const void *Decoder);
322
323
324 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
325 uint64_t Address, const void *Decoder);
326 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
327 uint64_t Address, const void *Decoder);
328 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
329 uint64_t Address, const void *Decoder);
330 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
331 uint64_t Address, const void *Decoder);
332 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
333 uint64_t Address, const void *Decoder);
334 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
335 uint64_t Address, const void *Decoder);
336 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
337 uint64_t Address, const void *Decoder);
338 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
339 uint64_t Address, const void *Decoder);
340 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
341 uint64_t Address, const void *Decoder);
342 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
343 uint64_t Address, const void *Decoder);
344 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
345 uint64_t Address, const void* Decoder);
346 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
347 uint64_t Address, const void* Decoder);
348 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
349 uint64_t Address, const void* Decoder);
350 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
351 uint64_t Address, const void* Decoder);
352 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
353 uint64_t Address, const void *Decoder);
354 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
355 uint64_t Address, const void *Decoder);
356 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
357 uint64_t Address, const void *Decoder);
358 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
359 uint64_t Address, const void *Decoder);
360 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
361 uint64_t Address, const void *Decoder);
362 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
363 uint64_t Address, const void *Decoder);
364 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
365 uint64_t Address, const void *Decoder);
366 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
367 uint64_t Address, const void *Decoder);
368 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
369 uint64_t Address, const void *Decoder);
370 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
371 uint64_t Address, const void *Decoder);
372 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
373 uint64_t Address, const void *Decoder);
374 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
375 uint64_t Address, const void *Decoder);
376 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
377 uint64_t Address, const void *Decoder);
378 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
379 uint64_t Address, const void *Decoder);
380 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
381 uint64_t Address, const void *Decoder);
382 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
383 uint64_t Address, const void *Decoder);
384 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
385 uint64_t Address, const void *Decoder);
386 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
387 uint64_t Address, const void *Decoder);
388 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
389 uint64_t Address, const void *Decoder);
390 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
391 uint64_t Address, const void *Decoder);
392 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
393 uint64_t Address, const void *Decoder);
394 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
395 uint64_t Address, const void *Decoder);
396
397 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
398 uint64_t Address, const void *Decoder);
399 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
400 uint64_t Address, const void *Decoder);
401 #include "ARMGenDisassemblerTables.inc"
402
createARMDisassembler(const Target & T,const MCSubtargetInfo & STI,MCContext & Ctx)403 static MCDisassembler *createARMDisassembler(const Target &T,
404 const MCSubtargetInfo &STI,
405 MCContext &Ctx) {
406 return new ARMDisassembler(STI, Ctx);
407 }
408
createThumbDisassembler(const Target & T,const MCSubtargetInfo & STI,MCContext & Ctx)409 static MCDisassembler *createThumbDisassembler(const Target &T,
410 const MCSubtargetInfo &STI,
411 MCContext &Ctx) {
412 return new ThumbDisassembler(STI, Ctx);
413 }
414
getInstruction(MCInst & MI,uint64_t & Size,const MemoryObject & Region,uint64_t Address,raw_ostream & os,raw_ostream & cs) const415 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
416 const MemoryObject &Region,
417 uint64_t Address,
418 raw_ostream &os,
419 raw_ostream &cs) const {
420 CommentStream = &cs;
421
422 uint8_t bytes[4];
423
424 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
425 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
426
427 // We want to read exactly 4 bytes of data.
428 if (Region.readBytes(Address, 4, bytes) == -1) {
429 Size = 0;
430 return MCDisassembler::Fail;
431 }
432
433 // Encoded as a small-endian 32-bit word in the stream.
434 uint32_t insn = (bytes[3] << 24) |
435 (bytes[2] << 16) |
436 (bytes[1] << 8) |
437 (bytes[0] << 0);
438
439 // Calling the auto-generated decoder function.
440 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn,
441 Address, this, STI);
442 if (result != MCDisassembler::Fail) {
443 Size = 4;
444 return result;
445 }
446
447 // VFP and NEON instructions, similarly, are shared between ARM
448 // and Thumb modes.
449 MI.clear();
450 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI);
451 if (result != MCDisassembler::Fail) {
452 Size = 4;
453 return result;
454 }
455
456 MI.clear();
457 result = decodeInstruction(DecoderTableVFPV832, MI, insn, Address, this, STI);
458 if (result != MCDisassembler::Fail) {
459 Size = 4;
460 return result;
461 }
462
463 MI.clear();
464 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
465 this, STI);
466 if (result != MCDisassembler::Fail) {
467 Size = 4;
468 // Add a fake predicate operand, because we share these instruction
469 // definitions with Thumb2 where these instructions are predicable.
470 if (!DecodePredicateOperand(MI, 0xE, Address, this))
471 return MCDisassembler::Fail;
472 return result;
473 }
474
475 MI.clear();
476 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address,
477 this, STI);
478 if (result != MCDisassembler::Fail) {
479 Size = 4;
480 // Add a fake predicate operand, because we share these instruction
481 // definitions with Thumb2 where these instructions are predicable.
482 if (!DecodePredicateOperand(MI, 0xE, Address, this))
483 return MCDisassembler::Fail;
484 return result;
485 }
486
487 MI.clear();
488 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address,
489 this, STI);
490 if (result != MCDisassembler::Fail) {
491 Size = 4;
492 // Add a fake predicate operand, because we share these instruction
493 // definitions with Thumb2 where these instructions are predicable.
494 if (!DecodePredicateOperand(MI, 0xE, Address, this))
495 return MCDisassembler::Fail;
496 return result;
497 }
498
499 MI.clear();
500 result = decodeInstruction(DecoderTablev8NEON32, MI, insn, Address,
501 this, STI);
502 if (result != MCDisassembler::Fail) {
503 Size = 4;
504 return result;
505 }
506
507 MI.clear();
508 result = decodeInstruction(DecoderTablev8Crypto32, MI, insn, Address,
509 this, STI);
510 if (result != MCDisassembler::Fail) {
511 Size = 4;
512 return result;
513 }
514
515 MI.clear();
516 Size = 0;
517 return MCDisassembler::Fail;
518 }
519
520 namespace llvm {
521 extern const MCInstrDesc ARMInsts[];
522 }
523
524 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
525 /// immediate Value in the MCInst. The immediate Value has had any PC
526 /// adjustment made by the caller. If the instruction is a branch instruction
527 /// then isBranch is true, else false. If the getOpInfo() function was set as
528 /// part of the setupForSymbolicDisassembly() call then that function is called
529 /// to get any symbolic information at the Address for this instruction. If
530 /// that returns non-zero then the symbolic information it returns is used to
531 /// create an MCExpr and that is added as an operand to the MCInst. If
532 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
533 /// Value is done and if a symbol is found an MCExpr is created with that, else
534 /// an MCExpr with Value is created. This function returns true if it adds an
535 /// operand to the MCInst and false otherwise.
tryAddingSymbolicOperand(uint64_t Address,int32_t Value,bool isBranch,uint64_t InstSize,MCInst & MI,const void * Decoder)536 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
537 bool isBranch, uint64_t InstSize,
538 MCInst &MI, const void *Decoder) {
539 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
540 // FIXME: Does it make sense for value to be negative?
541 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
542 /* Offset */ 0, InstSize);
543 }
544
545 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
546 /// referenced by a load instruction with the base register that is the Pc.
547 /// These can often be values in a literal pool near the Address of the
548 /// instruction. The Address of the instruction and its immediate Value are
549 /// used as a possible literal pool entry. The SymbolLookUp call back will
550 /// return the name of a symbol referenced by the literal pool's entry if
551 /// the referenced address is that of a symbol. Or it will return a pointer to
552 /// a literal 'C' string if the referenced address of the literal pool's entry
553 /// is an address into a section with 'C' string literals.
tryAddingPcLoadReferenceComment(uint64_t Address,int Value,const void * Decoder)554 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
555 const void *Decoder) {
556 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
557 Dis->tryAddingPcLoadReferenceComment(Value, Address);
558 }
559
560 // Thumb1 instructions don't have explicit S bits. Rather, they
561 // implicitly set CPSR. Since it's not represented in the encoding, the
562 // auto-generated decoder won't inject the CPSR operand. We need to fix
563 // that as a post-pass.
AddThumb1SBit(MCInst & MI,bool InITBlock)564 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
565 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
566 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
567 MCInst::iterator I = MI.begin();
568 for (unsigned i = 0; i < NumOps; ++i, ++I) {
569 if (I == MI.end()) break;
570 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
571 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
572 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
573 return;
574 }
575 }
576
577 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
578 }
579
580 // Most Thumb instructions don't have explicit predicates in the
581 // encoding, but rather get their predicates from IT context. We need
582 // to fix up the predicate operands using this context information as a
583 // post-pass.
584 MCDisassembler::DecodeStatus
AddThumbPredicate(MCInst & MI) const585 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
586 MCDisassembler::DecodeStatus S = Success;
587
588 // A few instructions actually have predicates encoded in them. Don't
589 // try to overwrite it if we're seeing one of those.
590 switch (MI.getOpcode()) {
591 case ARM::tBcc:
592 case ARM::t2Bcc:
593 case ARM::tCBZ:
594 case ARM::tCBNZ:
595 case ARM::tCPS:
596 case ARM::t2CPS3p:
597 case ARM::t2CPS2p:
598 case ARM::t2CPS1p:
599 case ARM::tMOVSr:
600 case ARM::tSETEND:
601 // Some instructions (mostly conditional branches) are not
602 // allowed in IT blocks.
603 if (ITBlock.instrInITBlock())
604 S = SoftFail;
605 else
606 return Success;
607 break;
608 case ARM::tB:
609 case ARM::t2B:
610 case ARM::t2TBB:
611 case ARM::t2TBH:
612 // Some instructions (mostly unconditional branches) can
613 // only appears at the end of, or outside of, an IT.
614 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
615 S = SoftFail;
616 break;
617 default:
618 break;
619 }
620
621 // If we're in an IT block, base the predicate on that. Otherwise,
622 // assume a predicate of AL.
623 unsigned CC;
624 CC = ITBlock.getITCC();
625 if (CC == 0xF)
626 CC = ARMCC::AL;
627 if (ITBlock.instrInITBlock())
628 ITBlock.advanceITState();
629
630 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
631 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
632 MCInst::iterator I = MI.begin();
633 for (unsigned i = 0; i < NumOps; ++i, ++I) {
634 if (I == MI.end()) break;
635 if (OpInfo[i].isPredicate()) {
636 I = MI.insert(I, MCOperand::CreateImm(CC));
637 ++I;
638 if (CC == ARMCC::AL)
639 MI.insert(I, MCOperand::CreateReg(0));
640 else
641 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
642 return S;
643 }
644 }
645
646 I = MI.insert(I, MCOperand::CreateImm(CC));
647 ++I;
648 if (CC == ARMCC::AL)
649 MI.insert(I, MCOperand::CreateReg(0));
650 else
651 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
652
653 return S;
654 }
655
656 // Thumb VFP instructions are a special case. Because we share their
657 // encodings between ARM and Thumb modes, and they are predicable in ARM
658 // mode, the auto-generated decoder will give them an (incorrect)
659 // predicate operand. We need to rewrite these operands based on the IT
660 // context as a post-pass.
UpdateThumbVFPPredicate(MCInst & MI) const661 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
662 unsigned CC;
663 CC = ITBlock.getITCC();
664 if (ITBlock.instrInITBlock())
665 ITBlock.advanceITState();
666
667 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
668 MCInst::iterator I = MI.begin();
669 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
670 for (unsigned i = 0; i < NumOps; ++i, ++I) {
671 if (OpInfo[i].isPredicate() ) {
672 I->setImm(CC);
673 ++I;
674 if (CC == ARMCC::AL)
675 I->setReg(0);
676 else
677 I->setReg(ARM::CPSR);
678 return;
679 }
680 }
681 }
682
getInstruction(MCInst & MI,uint64_t & Size,const MemoryObject & Region,uint64_t Address,raw_ostream & os,raw_ostream & cs) const683 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
684 const MemoryObject &Region,
685 uint64_t Address,
686 raw_ostream &os,
687 raw_ostream &cs) const {
688 CommentStream = &cs;
689
690 uint8_t bytes[4];
691
692 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
693 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
694
695 // We want to read exactly 2 bytes of data.
696 if (Region.readBytes(Address, 2, bytes) == -1) {
697 Size = 0;
698 return MCDisassembler::Fail;
699 }
700
701 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
702 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16,
703 Address, this, STI);
704 if (result != MCDisassembler::Fail) {
705 Size = 2;
706 Check(result, AddThumbPredicate(MI));
707 return result;
708 }
709
710 MI.clear();
711 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16,
712 Address, this, STI);
713 if (result) {
714 Size = 2;
715 bool InITBlock = ITBlock.instrInITBlock();
716 Check(result, AddThumbPredicate(MI));
717 AddThumb1SBit(MI, InITBlock);
718 return result;
719 }
720
721 MI.clear();
722 result = decodeInstruction(DecoderTableThumb216, MI, insn16,
723 Address, this, STI);
724 if (result != MCDisassembler::Fail) {
725 Size = 2;
726
727 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
728 // the Thumb predicate.
729 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
730 result = MCDisassembler::SoftFail;
731
732 Check(result, AddThumbPredicate(MI));
733
734 // If we find an IT instruction, we need to parse its condition
735 // code and mask operands so that we can apply them correctly
736 // to the subsequent instructions.
737 if (MI.getOpcode() == ARM::t2IT) {
738
739 unsigned Firstcond = MI.getOperand(0).getImm();
740 unsigned Mask = MI.getOperand(1).getImm();
741 ITBlock.setITState(Firstcond, Mask);
742 }
743
744 return result;
745 }
746
747 // We want to read exactly 4 bytes of data.
748 if (Region.readBytes(Address, 4, bytes) == -1) {
749 Size = 0;
750 return MCDisassembler::Fail;
751 }
752
753 uint32_t insn32 = (bytes[3] << 8) |
754 (bytes[2] << 0) |
755 (bytes[1] << 24) |
756 (bytes[0] << 16);
757 MI.clear();
758 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address,
759 this, STI);
760 if (result != MCDisassembler::Fail) {
761 Size = 4;
762 bool InITBlock = ITBlock.instrInITBlock();
763 Check(result, AddThumbPredicate(MI));
764 AddThumb1SBit(MI, InITBlock);
765 return result;
766 }
767
768 MI.clear();
769 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address,
770 this, STI);
771 if (result != MCDisassembler::Fail) {
772 Size = 4;
773 Check(result, AddThumbPredicate(MI));
774 return result;
775 }
776
777 if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
778 MI.clear();
779 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
780 if (result != MCDisassembler::Fail) {
781 Size = 4;
782 UpdateThumbVFPPredicate(MI);
783 return result;
784 }
785 }
786
787 MI.clear();
788 result = decodeInstruction(DecoderTableVFPV832, MI, insn32, Address, this, STI);
789 if (result != MCDisassembler::Fail) {
790 Size = 4;
791 return result;
792 }
793
794 if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
795 MI.clear();
796 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
797 this, STI);
798 if (result != MCDisassembler::Fail) {
799 Size = 4;
800 Check(result, AddThumbPredicate(MI));
801 return result;
802 }
803 }
804
805 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
806 MI.clear();
807 uint32_t NEONLdStInsn = insn32;
808 NEONLdStInsn &= 0xF0FFFFFF;
809 NEONLdStInsn |= 0x04000000;
810 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
811 Address, this, STI);
812 if (result != MCDisassembler::Fail) {
813 Size = 4;
814 Check(result, AddThumbPredicate(MI));
815 return result;
816 }
817 }
818
819 if (fieldFromInstruction(insn32, 24, 4) == 0xF) {
820 MI.clear();
821 uint32_t NEONDataInsn = insn32;
822 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
823 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
824 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
825 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
826 Address, this, STI);
827 if (result != MCDisassembler::Fail) {
828 Size = 4;
829 Check(result, AddThumbPredicate(MI));
830 return result;
831 }
832
833 MI.clear();
834 uint32_t NEONCryptoInsn = insn32;
835 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
836 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
837 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
838 result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
839 Address, this, STI);
840 if (result != MCDisassembler::Fail) {
841 Size = 4;
842 return result;
843 }
844
845 MI.clear();
846 uint32_t NEONv8Insn = insn32;
847 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
848 result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
849 this, STI);
850 if (result != MCDisassembler::Fail) {
851 Size = 4;
852 return result;
853 }
854 }
855
856 MI.clear();
857 Size = 0;
858 return MCDisassembler::Fail;
859 }
860
861
LLVMInitializeARMDisassembler()862 extern "C" void LLVMInitializeARMDisassembler() {
863 TargetRegistry::RegisterMCDisassembler(TheARMLETarget,
864 createARMDisassembler);
865 TargetRegistry::RegisterMCDisassembler(TheARMBETarget,
866 createARMDisassembler);
867 TargetRegistry::RegisterMCDisassembler(TheThumbLETarget,
868 createThumbDisassembler);
869 TargetRegistry::RegisterMCDisassembler(TheThumbBETarget,
870 createThumbDisassembler);
871 }
872
873 static const uint16_t GPRDecoderTable[] = {
874 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
875 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
876 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
877 ARM::R12, ARM::SP, ARM::LR, ARM::PC
878 };
879
DecodeGPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)880 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
881 uint64_t Address, const void *Decoder) {
882 if (RegNo > 15)
883 return MCDisassembler::Fail;
884
885 unsigned Register = GPRDecoderTable[RegNo];
886 Inst.addOperand(MCOperand::CreateReg(Register));
887 return MCDisassembler::Success;
888 }
889
890 static DecodeStatus
DecodeGPRnopcRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)891 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
892 uint64_t Address, const void *Decoder) {
893 DecodeStatus S = MCDisassembler::Success;
894
895 if (RegNo == 15)
896 S = MCDisassembler::SoftFail;
897
898 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
899
900 return S;
901 }
902
903 static DecodeStatus
DecodeGPRwithAPSRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)904 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
905 uint64_t Address, const void *Decoder) {
906 DecodeStatus S = MCDisassembler::Success;
907
908 if (RegNo == 15)
909 {
910 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
911 return MCDisassembler::Success;
912 }
913
914 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
915 return S;
916 }
917
DecodetGPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)918 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
919 uint64_t Address, const void *Decoder) {
920 if (RegNo > 7)
921 return MCDisassembler::Fail;
922 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
923 }
924
925 static const uint16_t GPRPairDecoderTable[] = {
926 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
927 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
928 };
929
DecodeGPRPairRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)930 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
931 uint64_t Address, const void *Decoder) {
932 DecodeStatus S = MCDisassembler::Success;
933
934 if (RegNo > 13)
935 return MCDisassembler::Fail;
936
937 if ((RegNo & 1) || RegNo == 0xe)
938 S = MCDisassembler::SoftFail;
939
940 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
941 Inst.addOperand(MCOperand::CreateReg(RegisterPair));
942 return S;
943 }
944
DecodetcGPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)945 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
946 uint64_t Address, const void *Decoder) {
947 unsigned Register = 0;
948 switch (RegNo) {
949 case 0:
950 Register = ARM::R0;
951 break;
952 case 1:
953 Register = ARM::R1;
954 break;
955 case 2:
956 Register = ARM::R2;
957 break;
958 case 3:
959 Register = ARM::R3;
960 break;
961 case 9:
962 Register = ARM::R9;
963 break;
964 case 12:
965 Register = ARM::R12;
966 break;
967 default:
968 return MCDisassembler::Fail;
969 }
970
971 Inst.addOperand(MCOperand::CreateReg(Register));
972 return MCDisassembler::Success;
973 }
974
DecoderGPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)975 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
976 uint64_t Address, const void *Decoder) {
977 DecodeStatus S = MCDisassembler::Success;
978 if (RegNo == 13 || RegNo == 15)
979 S = MCDisassembler::SoftFail;
980 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
981 return S;
982 }
983
984 static const uint16_t SPRDecoderTable[] = {
985 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
986 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
987 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
988 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
989 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
990 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
991 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
992 ARM::S28, ARM::S29, ARM::S30, ARM::S31
993 };
994
DecodeSPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)995 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
996 uint64_t Address, const void *Decoder) {
997 if (RegNo > 31)
998 return MCDisassembler::Fail;
999
1000 unsigned Register = SPRDecoderTable[RegNo];
1001 Inst.addOperand(MCOperand::CreateReg(Register));
1002 return MCDisassembler::Success;
1003 }
1004
1005 static const uint16_t DPRDecoderTable[] = {
1006 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1007 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1008 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1009 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1010 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1011 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1012 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1013 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1014 };
1015
DecodeDPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1016 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1017 uint64_t Address, const void *Decoder) {
1018 if (RegNo > 31)
1019 return MCDisassembler::Fail;
1020
1021 unsigned Register = DPRDecoderTable[RegNo];
1022 Inst.addOperand(MCOperand::CreateReg(Register));
1023 return MCDisassembler::Success;
1024 }
1025
DecodeDPR_8RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1026 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1027 uint64_t Address, const void *Decoder) {
1028 if (RegNo > 7)
1029 return MCDisassembler::Fail;
1030 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1031 }
1032
1033 static DecodeStatus
DecodeDPR_VFP2RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1034 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1035 uint64_t Address, const void *Decoder) {
1036 if (RegNo > 15)
1037 return MCDisassembler::Fail;
1038 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1039 }
1040
1041 static const uint16_t QPRDecoderTable[] = {
1042 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1043 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1044 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1045 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1046 };
1047
1048
DecodeQPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1049 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1050 uint64_t Address, const void *Decoder) {
1051 if (RegNo > 31 || (RegNo & 1) != 0)
1052 return MCDisassembler::Fail;
1053 RegNo >>= 1;
1054
1055 unsigned Register = QPRDecoderTable[RegNo];
1056 Inst.addOperand(MCOperand::CreateReg(Register));
1057 return MCDisassembler::Success;
1058 }
1059
1060 static const uint16_t DPairDecoderTable[] = {
1061 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1062 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1063 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1064 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1065 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1066 ARM::Q15
1067 };
1068
DecodeDPairRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1069 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1070 uint64_t Address, const void *Decoder) {
1071 if (RegNo > 30)
1072 return MCDisassembler::Fail;
1073
1074 unsigned Register = DPairDecoderTable[RegNo];
1075 Inst.addOperand(MCOperand::CreateReg(Register));
1076 return MCDisassembler::Success;
1077 }
1078
1079 static const uint16_t DPairSpacedDecoderTable[] = {
1080 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1081 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1082 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1083 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1084 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1085 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1086 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1087 ARM::D28_D30, ARM::D29_D31
1088 };
1089
DecodeDPairSpacedRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1090 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1091 unsigned RegNo,
1092 uint64_t Address,
1093 const void *Decoder) {
1094 if (RegNo > 29)
1095 return MCDisassembler::Fail;
1096
1097 unsigned Register = DPairSpacedDecoderTable[RegNo];
1098 Inst.addOperand(MCOperand::CreateReg(Register));
1099 return MCDisassembler::Success;
1100 }
1101
DecodePredicateOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1102 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1103 uint64_t Address, const void *Decoder) {
1104 if (Val == 0xF) return MCDisassembler::Fail;
1105 // AL predicate is not allowed on Thumb1 branches.
1106 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1107 return MCDisassembler::Fail;
1108 Inst.addOperand(MCOperand::CreateImm(Val));
1109 if (Val == ARMCC::AL) {
1110 Inst.addOperand(MCOperand::CreateReg(0));
1111 } else
1112 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1113 return MCDisassembler::Success;
1114 }
1115
DecodeCCOutOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1116 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1117 uint64_t Address, const void *Decoder) {
1118 if (Val)
1119 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1120 else
1121 Inst.addOperand(MCOperand::CreateReg(0));
1122 return MCDisassembler::Success;
1123 }
1124
DecodeSOImmOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1125 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
1126 uint64_t Address, const void *Decoder) {
1127 uint32_t imm = Val & 0xFF;
1128 uint32_t rot = (Val & 0xF00) >> 7;
1129 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
1130 Inst.addOperand(MCOperand::CreateImm(rot_imm));
1131 return MCDisassembler::Success;
1132 }
1133
DecodeSORegImmOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1134 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1135 uint64_t Address, const void *Decoder) {
1136 DecodeStatus S = MCDisassembler::Success;
1137
1138 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1139 unsigned type = fieldFromInstruction(Val, 5, 2);
1140 unsigned imm = fieldFromInstruction(Val, 7, 5);
1141
1142 // Register-immediate
1143 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1144 return MCDisassembler::Fail;
1145
1146 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1147 switch (type) {
1148 case 0:
1149 Shift = ARM_AM::lsl;
1150 break;
1151 case 1:
1152 Shift = ARM_AM::lsr;
1153 break;
1154 case 2:
1155 Shift = ARM_AM::asr;
1156 break;
1157 case 3:
1158 Shift = ARM_AM::ror;
1159 break;
1160 }
1161
1162 if (Shift == ARM_AM::ror && imm == 0)
1163 Shift = ARM_AM::rrx;
1164
1165 unsigned Op = Shift | (imm << 3);
1166 Inst.addOperand(MCOperand::CreateImm(Op));
1167
1168 return S;
1169 }
1170
DecodeSORegRegOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1171 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1172 uint64_t Address, const void *Decoder) {
1173 DecodeStatus S = MCDisassembler::Success;
1174
1175 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1176 unsigned type = fieldFromInstruction(Val, 5, 2);
1177 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1178
1179 // Register-register
1180 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1181 return MCDisassembler::Fail;
1182 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1183 return MCDisassembler::Fail;
1184
1185 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1186 switch (type) {
1187 case 0:
1188 Shift = ARM_AM::lsl;
1189 break;
1190 case 1:
1191 Shift = ARM_AM::lsr;
1192 break;
1193 case 2:
1194 Shift = ARM_AM::asr;
1195 break;
1196 case 3:
1197 Shift = ARM_AM::ror;
1198 break;
1199 }
1200
1201 Inst.addOperand(MCOperand::CreateImm(Shift));
1202
1203 return S;
1204 }
1205
DecodeRegListOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1206 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1207 uint64_t Address, const void *Decoder) {
1208 DecodeStatus S = MCDisassembler::Success;
1209
1210 bool NeedDisjointWriteback = false;
1211 unsigned WritebackReg = 0;
1212 switch (Inst.getOpcode()) {
1213 default:
1214 break;
1215 case ARM::LDMIA_UPD:
1216 case ARM::LDMDB_UPD:
1217 case ARM::LDMIB_UPD:
1218 case ARM::LDMDA_UPD:
1219 case ARM::t2LDMIA_UPD:
1220 case ARM::t2LDMDB_UPD:
1221 case ARM::t2STMIA_UPD:
1222 case ARM::t2STMDB_UPD:
1223 NeedDisjointWriteback = true;
1224 WritebackReg = Inst.getOperand(0).getReg();
1225 break;
1226 }
1227
1228 // Empty register lists are not allowed.
1229 if (Val == 0) return MCDisassembler::Fail;
1230 for (unsigned i = 0; i < 16; ++i) {
1231 if (Val & (1 << i)) {
1232 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1233 return MCDisassembler::Fail;
1234 // Writeback not allowed if Rn is in the target list.
1235 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1236 Check(S, MCDisassembler::SoftFail);
1237 }
1238 }
1239
1240 return S;
1241 }
1242
DecodeSPRRegListOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1243 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1244 uint64_t Address, const void *Decoder) {
1245 DecodeStatus S = MCDisassembler::Success;
1246
1247 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1248 unsigned regs = fieldFromInstruction(Val, 0, 8);
1249
1250 // In case of unpredictable encoding, tweak the operands.
1251 if (regs == 0 || (Vd + regs) > 32) {
1252 regs = Vd + regs > 32 ? 32 - Vd : regs;
1253 regs = std::max( 1u, regs);
1254 S = MCDisassembler::SoftFail;
1255 }
1256
1257 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1258 return MCDisassembler::Fail;
1259 for (unsigned i = 0; i < (regs - 1); ++i) {
1260 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1261 return MCDisassembler::Fail;
1262 }
1263
1264 return S;
1265 }
1266
DecodeDPRRegListOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1267 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1268 uint64_t Address, const void *Decoder) {
1269 DecodeStatus S = MCDisassembler::Success;
1270
1271 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1272 unsigned regs = fieldFromInstruction(Val, 1, 7);
1273
1274 // In case of unpredictable encoding, tweak the operands.
1275 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1276 regs = Vd + regs > 32 ? 32 - Vd : regs;
1277 regs = std::max( 1u, regs);
1278 regs = std::min(16u, regs);
1279 S = MCDisassembler::SoftFail;
1280 }
1281
1282 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1283 return MCDisassembler::Fail;
1284 for (unsigned i = 0; i < (regs - 1); ++i) {
1285 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1286 return MCDisassembler::Fail;
1287 }
1288
1289 return S;
1290 }
1291
DecodeBitfieldMaskOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1292 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1293 uint64_t Address, const void *Decoder) {
1294 // This operand encodes a mask of contiguous zeros between a specified MSB
1295 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1296 // the mask of all bits LSB-and-lower, and then xor them to create
1297 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1298 // create the final mask.
1299 unsigned msb = fieldFromInstruction(Val, 5, 5);
1300 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1301
1302 DecodeStatus S = MCDisassembler::Success;
1303 if (lsb > msb) {
1304 Check(S, MCDisassembler::SoftFail);
1305 // The check above will cause the warning for the "potentially undefined
1306 // instruction encoding" but we can't build a bad MCOperand value here
1307 // with a lsb > msb or else printing the MCInst will cause a crash.
1308 lsb = msb;
1309 }
1310
1311 uint32_t msb_mask = 0xFFFFFFFF;
1312 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1313 uint32_t lsb_mask = (1U << lsb) - 1;
1314
1315 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
1316 return S;
1317 }
1318
DecodeCopMemInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1319 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1320 uint64_t Address, const void *Decoder) {
1321 DecodeStatus S = MCDisassembler::Success;
1322
1323 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1324 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1325 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1326 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1327 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1328 unsigned U = fieldFromInstruction(Insn, 23, 1);
1329
1330 switch (Inst.getOpcode()) {
1331 case ARM::LDC_OFFSET:
1332 case ARM::LDC_PRE:
1333 case ARM::LDC_POST:
1334 case ARM::LDC_OPTION:
1335 case ARM::LDCL_OFFSET:
1336 case ARM::LDCL_PRE:
1337 case ARM::LDCL_POST:
1338 case ARM::LDCL_OPTION:
1339 case ARM::STC_OFFSET:
1340 case ARM::STC_PRE:
1341 case ARM::STC_POST:
1342 case ARM::STC_OPTION:
1343 case ARM::STCL_OFFSET:
1344 case ARM::STCL_PRE:
1345 case ARM::STCL_POST:
1346 case ARM::STCL_OPTION:
1347 case ARM::t2LDC_OFFSET:
1348 case ARM::t2LDC_PRE:
1349 case ARM::t2LDC_POST:
1350 case ARM::t2LDC_OPTION:
1351 case ARM::t2LDCL_OFFSET:
1352 case ARM::t2LDCL_PRE:
1353 case ARM::t2LDCL_POST:
1354 case ARM::t2LDCL_OPTION:
1355 case ARM::t2STC_OFFSET:
1356 case ARM::t2STC_PRE:
1357 case ARM::t2STC_POST:
1358 case ARM::t2STC_OPTION:
1359 case ARM::t2STCL_OFFSET:
1360 case ARM::t2STCL_PRE:
1361 case ARM::t2STCL_POST:
1362 case ARM::t2STCL_OPTION:
1363 if (coproc == 0xA || coproc == 0xB)
1364 return MCDisassembler::Fail;
1365 break;
1366 default:
1367 break;
1368 }
1369
1370 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
1371 .getFeatureBits();
1372 if ((featureBits & ARM::HasV8Ops) && (coproc != 14))
1373 return MCDisassembler::Fail;
1374
1375 Inst.addOperand(MCOperand::CreateImm(coproc));
1376 Inst.addOperand(MCOperand::CreateImm(CRd));
1377 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1378 return MCDisassembler::Fail;
1379
1380 switch (Inst.getOpcode()) {
1381 case ARM::t2LDC2_OFFSET:
1382 case ARM::t2LDC2L_OFFSET:
1383 case ARM::t2LDC2_PRE:
1384 case ARM::t2LDC2L_PRE:
1385 case ARM::t2STC2_OFFSET:
1386 case ARM::t2STC2L_OFFSET:
1387 case ARM::t2STC2_PRE:
1388 case ARM::t2STC2L_PRE:
1389 case ARM::LDC2_OFFSET:
1390 case ARM::LDC2L_OFFSET:
1391 case ARM::LDC2_PRE:
1392 case ARM::LDC2L_PRE:
1393 case ARM::STC2_OFFSET:
1394 case ARM::STC2L_OFFSET:
1395 case ARM::STC2_PRE:
1396 case ARM::STC2L_PRE:
1397 case ARM::t2LDC_OFFSET:
1398 case ARM::t2LDCL_OFFSET:
1399 case ARM::t2LDC_PRE:
1400 case ARM::t2LDCL_PRE:
1401 case ARM::t2STC_OFFSET:
1402 case ARM::t2STCL_OFFSET:
1403 case ARM::t2STC_PRE:
1404 case ARM::t2STCL_PRE:
1405 case ARM::LDC_OFFSET:
1406 case ARM::LDCL_OFFSET:
1407 case ARM::LDC_PRE:
1408 case ARM::LDCL_PRE:
1409 case ARM::STC_OFFSET:
1410 case ARM::STCL_OFFSET:
1411 case ARM::STC_PRE:
1412 case ARM::STCL_PRE:
1413 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1414 Inst.addOperand(MCOperand::CreateImm(imm));
1415 break;
1416 case ARM::t2LDC2_POST:
1417 case ARM::t2LDC2L_POST:
1418 case ARM::t2STC2_POST:
1419 case ARM::t2STC2L_POST:
1420 case ARM::LDC2_POST:
1421 case ARM::LDC2L_POST:
1422 case ARM::STC2_POST:
1423 case ARM::STC2L_POST:
1424 case ARM::t2LDC_POST:
1425 case ARM::t2LDCL_POST:
1426 case ARM::t2STC_POST:
1427 case ARM::t2STCL_POST:
1428 case ARM::LDC_POST:
1429 case ARM::LDCL_POST:
1430 case ARM::STC_POST:
1431 case ARM::STCL_POST:
1432 imm |= U << 8;
1433 // fall through.
1434 default:
1435 // The 'option' variant doesn't encode 'U' in the immediate since
1436 // the immediate is unsigned [0,255].
1437 Inst.addOperand(MCOperand::CreateImm(imm));
1438 break;
1439 }
1440
1441 switch (Inst.getOpcode()) {
1442 case ARM::LDC_OFFSET:
1443 case ARM::LDC_PRE:
1444 case ARM::LDC_POST:
1445 case ARM::LDC_OPTION:
1446 case ARM::LDCL_OFFSET:
1447 case ARM::LDCL_PRE:
1448 case ARM::LDCL_POST:
1449 case ARM::LDCL_OPTION:
1450 case ARM::STC_OFFSET:
1451 case ARM::STC_PRE:
1452 case ARM::STC_POST:
1453 case ARM::STC_OPTION:
1454 case ARM::STCL_OFFSET:
1455 case ARM::STCL_PRE:
1456 case ARM::STCL_POST:
1457 case ARM::STCL_OPTION:
1458 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1459 return MCDisassembler::Fail;
1460 break;
1461 default:
1462 break;
1463 }
1464
1465 return S;
1466 }
1467
1468 static DecodeStatus
DecodeAddrMode2IdxInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1469 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1470 uint64_t Address, const void *Decoder) {
1471 DecodeStatus S = MCDisassembler::Success;
1472
1473 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1474 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1475 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1476 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1477 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1478 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1479 unsigned P = fieldFromInstruction(Insn, 24, 1);
1480 unsigned W = fieldFromInstruction(Insn, 21, 1);
1481
1482 // On stores, the writeback operand precedes Rt.
1483 switch (Inst.getOpcode()) {
1484 case ARM::STR_POST_IMM:
1485 case ARM::STR_POST_REG:
1486 case ARM::STRB_POST_IMM:
1487 case ARM::STRB_POST_REG:
1488 case ARM::STRT_POST_REG:
1489 case ARM::STRT_POST_IMM:
1490 case ARM::STRBT_POST_REG:
1491 case ARM::STRBT_POST_IMM:
1492 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1493 return MCDisassembler::Fail;
1494 break;
1495 default:
1496 break;
1497 }
1498
1499 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1500 return MCDisassembler::Fail;
1501
1502 // On loads, the writeback operand comes after Rt.
1503 switch (Inst.getOpcode()) {
1504 case ARM::LDR_POST_IMM:
1505 case ARM::LDR_POST_REG:
1506 case ARM::LDRB_POST_IMM:
1507 case ARM::LDRB_POST_REG:
1508 case ARM::LDRBT_POST_REG:
1509 case ARM::LDRBT_POST_IMM:
1510 case ARM::LDRT_POST_REG:
1511 case ARM::LDRT_POST_IMM:
1512 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1513 return MCDisassembler::Fail;
1514 break;
1515 default:
1516 break;
1517 }
1518
1519 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1520 return MCDisassembler::Fail;
1521
1522 ARM_AM::AddrOpc Op = ARM_AM::add;
1523 if (!fieldFromInstruction(Insn, 23, 1))
1524 Op = ARM_AM::sub;
1525
1526 bool writeback = (P == 0) || (W == 1);
1527 unsigned idx_mode = 0;
1528 if (P && writeback)
1529 idx_mode = ARMII::IndexModePre;
1530 else if (!P && writeback)
1531 idx_mode = ARMII::IndexModePost;
1532
1533 if (writeback && (Rn == 15 || Rn == Rt))
1534 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1535
1536 if (reg) {
1537 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1538 return MCDisassembler::Fail;
1539 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1540 switch( fieldFromInstruction(Insn, 5, 2)) {
1541 case 0:
1542 Opc = ARM_AM::lsl;
1543 break;
1544 case 1:
1545 Opc = ARM_AM::lsr;
1546 break;
1547 case 2:
1548 Opc = ARM_AM::asr;
1549 break;
1550 case 3:
1551 Opc = ARM_AM::ror;
1552 break;
1553 default:
1554 return MCDisassembler::Fail;
1555 }
1556 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1557 if (Opc == ARM_AM::ror && amt == 0)
1558 Opc = ARM_AM::rrx;
1559 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1560
1561 Inst.addOperand(MCOperand::CreateImm(imm));
1562 } else {
1563 Inst.addOperand(MCOperand::CreateReg(0));
1564 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1565 Inst.addOperand(MCOperand::CreateImm(tmp));
1566 }
1567
1568 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1569 return MCDisassembler::Fail;
1570
1571 return S;
1572 }
1573
DecodeSORegMemOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)1574 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1575 uint64_t Address, const void *Decoder) {
1576 DecodeStatus S = MCDisassembler::Success;
1577
1578 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1579 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1580 unsigned type = fieldFromInstruction(Val, 5, 2);
1581 unsigned imm = fieldFromInstruction(Val, 7, 5);
1582 unsigned U = fieldFromInstruction(Val, 12, 1);
1583
1584 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1585 switch (type) {
1586 case 0:
1587 ShOp = ARM_AM::lsl;
1588 break;
1589 case 1:
1590 ShOp = ARM_AM::lsr;
1591 break;
1592 case 2:
1593 ShOp = ARM_AM::asr;
1594 break;
1595 case 3:
1596 ShOp = ARM_AM::ror;
1597 break;
1598 }
1599
1600 if (ShOp == ARM_AM::ror && imm == 0)
1601 ShOp = ARM_AM::rrx;
1602
1603 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1604 return MCDisassembler::Fail;
1605 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1606 return MCDisassembler::Fail;
1607 unsigned shift;
1608 if (U)
1609 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1610 else
1611 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1612 Inst.addOperand(MCOperand::CreateImm(shift));
1613
1614 return S;
1615 }
1616
1617 static DecodeStatus
DecodeAddrMode3Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1618 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1619 uint64_t Address, const void *Decoder) {
1620 DecodeStatus S = MCDisassembler::Success;
1621
1622 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1623 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1624 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1625 unsigned type = fieldFromInstruction(Insn, 22, 1);
1626 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1627 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1628 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1629 unsigned W = fieldFromInstruction(Insn, 21, 1);
1630 unsigned P = fieldFromInstruction(Insn, 24, 1);
1631 unsigned Rt2 = Rt + 1;
1632
1633 bool writeback = (W == 1) | (P == 0);
1634
1635 // For {LD,ST}RD, Rt must be even, else undefined.
1636 switch (Inst.getOpcode()) {
1637 case ARM::STRD:
1638 case ARM::STRD_PRE:
1639 case ARM::STRD_POST:
1640 case ARM::LDRD:
1641 case ARM::LDRD_PRE:
1642 case ARM::LDRD_POST:
1643 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1644 break;
1645 default:
1646 break;
1647 }
1648 switch (Inst.getOpcode()) {
1649 case ARM::STRD:
1650 case ARM::STRD_PRE:
1651 case ARM::STRD_POST:
1652 if (P == 0 && W == 1)
1653 S = MCDisassembler::SoftFail;
1654
1655 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1656 S = MCDisassembler::SoftFail;
1657 if (type && Rm == 15)
1658 S = MCDisassembler::SoftFail;
1659 if (Rt2 == 15)
1660 S = MCDisassembler::SoftFail;
1661 if (!type && fieldFromInstruction(Insn, 8, 4))
1662 S = MCDisassembler::SoftFail;
1663 break;
1664 case ARM::STRH:
1665 case ARM::STRH_PRE:
1666 case ARM::STRH_POST:
1667 if (Rt == 15)
1668 S = MCDisassembler::SoftFail;
1669 if (writeback && (Rn == 15 || Rn == Rt))
1670 S = MCDisassembler::SoftFail;
1671 if (!type && Rm == 15)
1672 S = MCDisassembler::SoftFail;
1673 break;
1674 case ARM::LDRD:
1675 case ARM::LDRD_PRE:
1676 case ARM::LDRD_POST:
1677 if (type && Rn == 15){
1678 if (Rt2 == 15)
1679 S = MCDisassembler::SoftFail;
1680 break;
1681 }
1682 if (P == 0 && W == 1)
1683 S = MCDisassembler::SoftFail;
1684 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1685 S = MCDisassembler::SoftFail;
1686 if (!type && writeback && Rn == 15)
1687 S = MCDisassembler::SoftFail;
1688 if (writeback && (Rn == Rt || Rn == Rt2))
1689 S = MCDisassembler::SoftFail;
1690 break;
1691 case ARM::LDRH:
1692 case ARM::LDRH_PRE:
1693 case ARM::LDRH_POST:
1694 if (type && Rn == 15){
1695 if (Rt == 15)
1696 S = MCDisassembler::SoftFail;
1697 break;
1698 }
1699 if (Rt == 15)
1700 S = MCDisassembler::SoftFail;
1701 if (!type && Rm == 15)
1702 S = MCDisassembler::SoftFail;
1703 if (!type && writeback && (Rn == 15 || Rn == Rt))
1704 S = MCDisassembler::SoftFail;
1705 break;
1706 case ARM::LDRSH:
1707 case ARM::LDRSH_PRE:
1708 case ARM::LDRSH_POST:
1709 case ARM::LDRSB:
1710 case ARM::LDRSB_PRE:
1711 case ARM::LDRSB_POST:
1712 if (type && Rn == 15){
1713 if (Rt == 15)
1714 S = MCDisassembler::SoftFail;
1715 break;
1716 }
1717 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1718 S = MCDisassembler::SoftFail;
1719 if (!type && (Rt == 15 || Rm == 15))
1720 S = MCDisassembler::SoftFail;
1721 if (!type && writeback && (Rn == 15 || Rn == Rt))
1722 S = MCDisassembler::SoftFail;
1723 break;
1724 default:
1725 break;
1726 }
1727
1728 if (writeback) { // Writeback
1729 if (P)
1730 U |= ARMII::IndexModePre << 9;
1731 else
1732 U |= ARMII::IndexModePost << 9;
1733
1734 // On stores, the writeback operand precedes Rt.
1735 switch (Inst.getOpcode()) {
1736 case ARM::STRD:
1737 case ARM::STRD_PRE:
1738 case ARM::STRD_POST:
1739 case ARM::STRH:
1740 case ARM::STRH_PRE:
1741 case ARM::STRH_POST:
1742 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1743 return MCDisassembler::Fail;
1744 break;
1745 default:
1746 break;
1747 }
1748 }
1749
1750 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1751 return MCDisassembler::Fail;
1752 switch (Inst.getOpcode()) {
1753 case ARM::STRD:
1754 case ARM::STRD_PRE:
1755 case ARM::STRD_POST:
1756 case ARM::LDRD:
1757 case ARM::LDRD_PRE:
1758 case ARM::LDRD_POST:
1759 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1760 return MCDisassembler::Fail;
1761 break;
1762 default:
1763 break;
1764 }
1765
1766 if (writeback) {
1767 // On loads, the writeback operand comes after Rt.
1768 switch (Inst.getOpcode()) {
1769 case ARM::LDRD:
1770 case ARM::LDRD_PRE:
1771 case ARM::LDRD_POST:
1772 case ARM::LDRH:
1773 case ARM::LDRH_PRE:
1774 case ARM::LDRH_POST:
1775 case ARM::LDRSH:
1776 case ARM::LDRSH_PRE:
1777 case ARM::LDRSH_POST:
1778 case ARM::LDRSB:
1779 case ARM::LDRSB_PRE:
1780 case ARM::LDRSB_POST:
1781 case ARM::LDRHTr:
1782 case ARM::LDRSBTr:
1783 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1784 return MCDisassembler::Fail;
1785 break;
1786 default:
1787 break;
1788 }
1789 }
1790
1791 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1792 return MCDisassembler::Fail;
1793
1794 if (type) {
1795 Inst.addOperand(MCOperand::CreateReg(0));
1796 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1797 } else {
1798 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1799 return MCDisassembler::Fail;
1800 Inst.addOperand(MCOperand::CreateImm(U));
1801 }
1802
1803 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1804 return MCDisassembler::Fail;
1805
1806 return S;
1807 }
1808
DecodeRFEInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1809 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1810 uint64_t Address, const void *Decoder) {
1811 DecodeStatus S = MCDisassembler::Success;
1812
1813 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1814 unsigned mode = fieldFromInstruction(Insn, 23, 2);
1815
1816 switch (mode) {
1817 case 0:
1818 mode = ARM_AM::da;
1819 break;
1820 case 1:
1821 mode = ARM_AM::ia;
1822 break;
1823 case 2:
1824 mode = ARM_AM::db;
1825 break;
1826 case 3:
1827 mode = ARM_AM::ib;
1828 break;
1829 }
1830
1831 Inst.addOperand(MCOperand::CreateImm(mode));
1832 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1833 return MCDisassembler::Fail;
1834
1835 return S;
1836 }
1837
DecodeQADDInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1838 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1839 uint64_t Address, const void *Decoder) {
1840 DecodeStatus S = MCDisassembler::Success;
1841
1842 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1843 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1844 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1845 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1846
1847 if (pred == 0xF)
1848 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1849
1850 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1851 return MCDisassembler::Fail;
1852 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1853 return MCDisassembler::Fail;
1854 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1855 return MCDisassembler::Fail;
1856 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1857 return MCDisassembler::Fail;
1858 return S;
1859 }
1860
DecodeMemMultipleWritebackInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1861 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
1862 unsigned Insn,
1863 uint64_t Address, const void *Decoder) {
1864 DecodeStatus S = MCDisassembler::Success;
1865
1866 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1867 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1868 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1869
1870 if (pred == 0xF) {
1871 // Ambiguous with RFE and SRS
1872 switch (Inst.getOpcode()) {
1873 case ARM::LDMDA:
1874 Inst.setOpcode(ARM::RFEDA);
1875 break;
1876 case ARM::LDMDA_UPD:
1877 Inst.setOpcode(ARM::RFEDA_UPD);
1878 break;
1879 case ARM::LDMDB:
1880 Inst.setOpcode(ARM::RFEDB);
1881 break;
1882 case ARM::LDMDB_UPD:
1883 Inst.setOpcode(ARM::RFEDB_UPD);
1884 break;
1885 case ARM::LDMIA:
1886 Inst.setOpcode(ARM::RFEIA);
1887 break;
1888 case ARM::LDMIA_UPD:
1889 Inst.setOpcode(ARM::RFEIA_UPD);
1890 break;
1891 case ARM::LDMIB:
1892 Inst.setOpcode(ARM::RFEIB);
1893 break;
1894 case ARM::LDMIB_UPD:
1895 Inst.setOpcode(ARM::RFEIB_UPD);
1896 break;
1897 case ARM::STMDA:
1898 Inst.setOpcode(ARM::SRSDA);
1899 break;
1900 case ARM::STMDA_UPD:
1901 Inst.setOpcode(ARM::SRSDA_UPD);
1902 break;
1903 case ARM::STMDB:
1904 Inst.setOpcode(ARM::SRSDB);
1905 break;
1906 case ARM::STMDB_UPD:
1907 Inst.setOpcode(ARM::SRSDB_UPD);
1908 break;
1909 case ARM::STMIA:
1910 Inst.setOpcode(ARM::SRSIA);
1911 break;
1912 case ARM::STMIA_UPD:
1913 Inst.setOpcode(ARM::SRSIA_UPD);
1914 break;
1915 case ARM::STMIB:
1916 Inst.setOpcode(ARM::SRSIB);
1917 break;
1918 case ARM::STMIB_UPD:
1919 Inst.setOpcode(ARM::SRSIB_UPD);
1920 break;
1921 default:
1922 return MCDisassembler::Fail;
1923 }
1924
1925 // For stores (which become SRS's, the only operand is the mode.
1926 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1927 // Check SRS encoding constraints
1928 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1929 fieldFromInstruction(Insn, 20, 1) == 0))
1930 return MCDisassembler::Fail;
1931
1932 Inst.addOperand(
1933 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
1934 return S;
1935 }
1936
1937 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1938 }
1939
1940 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1941 return MCDisassembler::Fail;
1942 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1943 return MCDisassembler::Fail; // Tied
1944 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1945 return MCDisassembler::Fail;
1946 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1947 return MCDisassembler::Fail;
1948
1949 return S;
1950 }
1951
DecodeCPSInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1952 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1953 uint64_t Address, const void *Decoder) {
1954 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1955 unsigned M = fieldFromInstruction(Insn, 17, 1);
1956 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1957 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1958
1959 DecodeStatus S = MCDisassembler::Success;
1960
1961 // This decoder is called from multiple location that do not check
1962 // the full encoding is valid before they do.
1963 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1964 fieldFromInstruction(Insn, 16, 1) != 0 ||
1965 fieldFromInstruction(Insn, 20, 8) != 0x10)
1966 return MCDisassembler::Fail;
1967
1968 // imod == '01' --> UNPREDICTABLE
1969 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1970 // return failure here. The '01' imod value is unprintable, so there's
1971 // nothing useful we could do even if we returned UNPREDICTABLE.
1972
1973 if (imod == 1) return MCDisassembler::Fail;
1974
1975 if (imod && M) {
1976 Inst.setOpcode(ARM::CPS3p);
1977 Inst.addOperand(MCOperand::CreateImm(imod));
1978 Inst.addOperand(MCOperand::CreateImm(iflags));
1979 Inst.addOperand(MCOperand::CreateImm(mode));
1980 } else if (imod && !M) {
1981 Inst.setOpcode(ARM::CPS2p);
1982 Inst.addOperand(MCOperand::CreateImm(imod));
1983 Inst.addOperand(MCOperand::CreateImm(iflags));
1984 if (mode) S = MCDisassembler::SoftFail;
1985 } else if (!imod && M) {
1986 Inst.setOpcode(ARM::CPS1p);
1987 Inst.addOperand(MCOperand::CreateImm(mode));
1988 if (iflags) S = MCDisassembler::SoftFail;
1989 } else {
1990 // imod == '00' && M == '0' --> UNPREDICTABLE
1991 Inst.setOpcode(ARM::CPS1p);
1992 Inst.addOperand(MCOperand::CreateImm(mode));
1993 S = MCDisassembler::SoftFail;
1994 }
1995
1996 return S;
1997 }
1998
DecodeT2CPSInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1999 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
2000 uint64_t Address, const void *Decoder) {
2001 unsigned imod = fieldFromInstruction(Insn, 9, 2);
2002 unsigned M = fieldFromInstruction(Insn, 8, 1);
2003 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2004 unsigned mode = fieldFromInstruction(Insn, 0, 5);
2005
2006 DecodeStatus S = MCDisassembler::Success;
2007
2008 // imod == '01' --> UNPREDICTABLE
2009 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2010 // return failure here. The '01' imod value is unprintable, so there's
2011 // nothing useful we could do even if we returned UNPREDICTABLE.
2012
2013 if (imod == 1) return MCDisassembler::Fail;
2014
2015 if (imod && M) {
2016 Inst.setOpcode(ARM::t2CPS3p);
2017 Inst.addOperand(MCOperand::CreateImm(imod));
2018 Inst.addOperand(MCOperand::CreateImm(iflags));
2019 Inst.addOperand(MCOperand::CreateImm(mode));
2020 } else if (imod && !M) {
2021 Inst.setOpcode(ARM::t2CPS2p);
2022 Inst.addOperand(MCOperand::CreateImm(imod));
2023 Inst.addOperand(MCOperand::CreateImm(iflags));
2024 if (mode) S = MCDisassembler::SoftFail;
2025 } else if (!imod && M) {
2026 Inst.setOpcode(ARM::t2CPS1p);
2027 Inst.addOperand(MCOperand::CreateImm(mode));
2028 if (iflags) S = MCDisassembler::SoftFail;
2029 } else {
2030 // imod == '00' && M == '0' --> this is a HINT instruction
2031 int imm = fieldFromInstruction(Insn, 0, 8);
2032 // HINT are defined only for immediate in [0..4]
2033 if(imm > 4) return MCDisassembler::Fail;
2034 Inst.setOpcode(ARM::t2HINT);
2035 Inst.addOperand(MCOperand::CreateImm(imm));
2036 }
2037
2038 return S;
2039 }
2040
DecodeT2MOVTWInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2041 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2042 uint64_t Address, const void *Decoder) {
2043 DecodeStatus S = MCDisassembler::Success;
2044
2045 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2046 unsigned imm = 0;
2047
2048 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2049 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2050 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2051 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2052
2053 if (Inst.getOpcode() == ARM::t2MOVTi16)
2054 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2055 return MCDisassembler::Fail;
2056 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2057 return MCDisassembler::Fail;
2058
2059 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2060 Inst.addOperand(MCOperand::CreateImm(imm));
2061
2062 return S;
2063 }
2064
DecodeArmMOVTWInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2065 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2066 uint64_t Address, const void *Decoder) {
2067 DecodeStatus S = MCDisassembler::Success;
2068
2069 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2070 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2071 unsigned imm = 0;
2072
2073 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2074 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2075
2076 if (Inst.getOpcode() == ARM::MOVTi16)
2077 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2078 return MCDisassembler::Fail;
2079
2080 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2081 return MCDisassembler::Fail;
2082
2083 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2084 Inst.addOperand(MCOperand::CreateImm(imm));
2085
2086 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2087 return MCDisassembler::Fail;
2088
2089 return S;
2090 }
2091
DecodeSMLAInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2092 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2093 uint64_t Address, const void *Decoder) {
2094 DecodeStatus S = MCDisassembler::Success;
2095
2096 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2097 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2098 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2099 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2100 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2101
2102 if (pred == 0xF)
2103 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2104
2105 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2106 return MCDisassembler::Fail;
2107 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2108 return MCDisassembler::Fail;
2109 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2110 return MCDisassembler::Fail;
2111 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2112 return MCDisassembler::Fail;
2113
2114 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2115 return MCDisassembler::Fail;
2116
2117 return S;
2118 }
2119
DecodeAddrModeImm12Operand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)2120 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2121 uint64_t Address, const void *Decoder) {
2122 DecodeStatus S = MCDisassembler::Success;
2123
2124 unsigned add = fieldFromInstruction(Val, 12, 1);
2125 unsigned imm = fieldFromInstruction(Val, 0, 12);
2126 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2127
2128 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2129 return MCDisassembler::Fail;
2130
2131 if (!add) imm *= -1;
2132 if (imm == 0 && !add) imm = INT32_MIN;
2133 Inst.addOperand(MCOperand::CreateImm(imm));
2134 if (Rn == 15)
2135 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2136
2137 return S;
2138 }
2139
DecodeAddrMode5Operand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)2140 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2141 uint64_t Address, const void *Decoder) {
2142 DecodeStatus S = MCDisassembler::Success;
2143
2144 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2145 unsigned U = fieldFromInstruction(Val, 8, 1);
2146 unsigned imm = fieldFromInstruction(Val, 0, 8);
2147
2148 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2149 return MCDisassembler::Fail;
2150
2151 if (U)
2152 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2153 else
2154 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2155
2156 return S;
2157 }
2158
DecodeAddrMode7Operand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)2159 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2160 uint64_t Address, const void *Decoder) {
2161 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2162 }
2163
2164 static DecodeStatus
DecodeT2BInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2165 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2166 uint64_t Address, const void *Decoder) {
2167 DecodeStatus Status = MCDisassembler::Success;
2168
2169 // Note the J1 and J2 values are from the encoded instruction. So here
2170 // change them to I1 and I2 values via as documented:
2171 // I1 = NOT(J1 EOR S);
2172 // I2 = NOT(J2 EOR S);
2173 // and build the imm32 with one trailing zero as documented:
2174 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2175 unsigned S = fieldFromInstruction(Insn, 26, 1);
2176 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2177 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2178 unsigned I1 = !(J1 ^ S);
2179 unsigned I2 = !(J2 ^ S);
2180 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2181 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2182 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2183 int imm32 = SignExtend32<25>(tmp << 1);
2184 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2185 true, 4, Inst, Decoder))
2186 Inst.addOperand(MCOperand::CreateImm(imm32));
2187
2188 return Status;
2189 }
2190
2191 static DecodeStatus
DecodeBranchImmInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2192 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2193 uint64_t Address, const void *Decoder) {
2194 DecodeStatus S = MCDisassembler::Success;
2195
2196 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2197 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2198
2199 if (pred == 0xF) {
2200 Inst.setOpcode(ARM::BLXi);
2201 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2202 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2203 true, 4, Inst, Decoder))
2204 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2205 return S;
2206 }
2207
2208 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2209 true, 4, Inst, Decoder))
2210 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2211 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2212 return MCDisassembler::Fail;
2213
2214 return S;
2215 }
2216
2217
DecodeAddrMode6Operand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)2218 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2219 uint64_t Address, const void *Decoder) {
2220 DecodeStatus S = MCDisassembler::Success;
2221
2222 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2223 unsigned align = fieldFromInstruction(Val, 4, 2);
2224
2225 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2226 return MCDisassembler::Fail;
2227 if (!align)
2228 Inst.addOperand(MCOperand::CreateImm(0));
2229 else
2230 Inst.addOperand(MCOperand::CreateImm(4 << align));
2231
2232 return S;
2233 }
2234
DecodeVLDInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2235 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2236 uint64_t Address, const void *Decoder) {
2237 DecodeStatus S = MCDisassembler::Success;
2238
2239 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2240 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2241 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2242 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2243 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2244 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2245
2246 // First output register
2247 switch (Inst.getOpcode()) {
2248 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2249 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2250 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2251 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2252 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2253 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2254 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2255 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2256 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2257 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2258 return MCDisassembler::Fail;
2259 break;
2260 case ARM::VLD2b16:
2261 case ARM::VLD2b32:
2262 case ARM::VLD2b8:
2263 case ARM::VLD2b16wb_fixed:
2264 case ARM::VLD2b16wb_register:
2265 case ARM::VLD2b32wb_fixed:
2266 case ARM::VLD2b32wb_register:
2267 case ARM::VLD2b8wb_fixed:
2268 case ARM::VLD2b8wb_register:
2269 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2270 return MCDisassembler::Fail;
2271 break;
2272 default:
2273 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2274 return MCDisassembler::Fail;
2275 }
2276
2277 // Second output register
2278 switch (Inst.getOpcode()) {
2279 case ARM::VLD3d8:
2280 case ARM::VLD3d16:
2281 case ARM::VLD3d32:
2282 case ARM::VLD3d8_UPD:
2283 case ARM::VLD3d16_UPD:
2284 case ARM::VLD3d32_UPD:
2285 case ARM::VLD4d8:
2286 case ARM::VLD4d16:
2287 case ARM::VLD4d32:
2288 case ARM::VLD4d8_UPD:
2289 case ARM::VLD4d16_UPD:
2290 case ARM::VLD4d32_UPD:
2291 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2292 return MCDisassembler::Fail;
2293 break;
2294 case ARM::VLD3q8:
2295 case ARM::VLD3q16:
2296 case ARM::VLD3q32:
2297 case ARM::VLD3q8_UPD:
2298 case ARM::VLD3q16_UPD:
2299 case ARM::VLD3q32_UPD:
2300 case ARM::VLD4q8:
2301 case ARM::VLD4q16:
2302 case ARM::VLD4q32:
2303 case ARM::VLD4q8_UPD:
2304 case ARM::VLD4q16_UPD:
2305 case ARM::VLD4q32_UPD:
2306 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2307 return MCDisassembler::Fail;
2308 default:
2309 break;
2310 }
2311
2312 // Third output register
2313 switch(Inst.getOpcode()) {
2314 case ARM::VLD3d8:
2315 case ARM::VLD3d16:
2316 case ARM::VLD3d32:
2317 case ARM::VLD3d8_UPD:
2318 case ARM::VLD3d16_UPD:
2319 case ARM::VLD3d32_UPD:
2320 case ARM::VLD4d8:
2321 case ARM::VLD4d16:
2322 case ARM::VLD4d32:
2323 case ARM::VLD4d8_UPD:
2324 case ARM::VLD4d16_UPD:
2325 case ARM::VLD4d32_UPD:
2326 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2327 return MCDisassembler::Fail;
2328 break;
2329 case ARM::VLD3q8:
2330 case ARM::VLD3q16:
2331 case ARM::VLD3q32:
2332 case ARM::VLD3q8_UPD:
2333 case ARM::VLD3q16_UPD:
2334 case ARM::VLD3q32_UPD:
2335 case ARM::VLD4q8:
2336 case ARM::VLD4q16:
2337 case ARM::VLD4q32:
2338 case ARM::VLD4q8_UPD:
2339 case ARM::VLD4q16_UPD:
2340 case ARM::VLD4q32_UPD:
2341 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2342 return MCDisassembler::Fail;
2343 break;
2344 default:
2345 break;
2346 }
2347
2348 // Fourth output register
2349 switch (Inst.getOpcode()) {
2350 case ARM::VLD4d8:
2351 case ARM::VLD4d16:
2352 case ARM::VLD4d32:
2353 case ARM::VLD4d8_UPD:
2354 case ARM::VLD4d16_UPD:
2355 case ARM::VLD4d32_UPD:
2356 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2357 return MCDisassembler::Fail;
2358 break;
2359 case ARM::VLD4q8:
2360 case ARM::VLD4q16:
2361 case ARM::VLD4q32:
2362 case ARM::VLD4q8_UPD:
2363 case ARM::VLD4q16_UPD:
2364 case ARM::VLD4q32_UPD:
2365 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2366 return MCDisassembler::Fail;
2367 break;
2368 default:
2369 break;
2370 }
2371
2372 // Writeback operand
2373 switch (Inst.getOpcode()) {
2374 case ARM::VLD1d8wb_fixed:
2375 case ARM::VLD1d16wb_fixed:
2376 case ARM::VLD1d32wb_fixed:
2377 case ARM::VLD1d64wb_fixed:
2378 case ARM::VLD1d8wb_register:
2379 case ARM::VLD1d16wb_register:
2380 case ARM::VLD1d32wb_register:
2381 case ARM::VLD1d64wb_register:
2382 case ARM::VLD1q8wb_fixed:
2383 case ARM::VLD1q16wb_fixed:
2384 case ARM::VLD1q32wb_fixed:
2385 case ARM::VLD1q64wb_fixed:
2386 case ARM::VLD1q8wb_register:
2387 case ARM::VLD1q16wb_register:
2388 case ARM::VLD1q32wb_register:
2389 case ARM::VLD1q64wb_register:
2390 case ARM::VLD1d8Twb_fixed:
2391 case ARM::VLD1d8Twb_register:
2392 case ARM::VLD1d16Twb_fixed:
2393 case ARM::VLD1d16Twb_register:
2394 case ARM::VLD1d32Twb_fixed:
2395 case ARM::VLD1d32Twb_register:
2396 case ARM::VLD1d64Twb_fixed:
2397 case ARM::VLD1d64Twb_register:
2398 case ARM::VLD1d8Qwb_fixed:
2399 case ARM::VLD1d8Qwb_register:
2400 case ARM::VLD1d16Qwb_fixed:
2401 case ARM::VLD1d16Qwb_register:
2402 case ARM::VLD1d32Qwb_fixed:
2403 case ARM::VLD1d32Qwb_register:
2404 case ARM::VLD1d64Qwb_fixed:
2405 case ARM::VLD1d64Qwb_register:
2406 case ARM::VLD2d8wb_fixed:
2407 case ARM::VLD2d16wb_fixed:
2408 case ARM::VLD2d32wb_fixed:
2409 case ARM::VLD2q8wb_fixed:
2410 case ARM::VLD2q16wb_fixed:
2411 case ARM::VLD2q32wb_fixed:
2412 case ARM::VLD2d8wb_register:
2413 case ARM::VLD2d16wb_register:
2414 case ARM::VLD2d32wb_register:
2415 case ARM::VLD2q8wb_register:
2416 case ARM::VLD2q16wb_register:
2417 case ARM::VLD2q32wb_register:
2418 case ARM::VLD2b8wb_fixed:
2419 case ARM::VLD2b16wb_fixed:
2420 case ARM::VLD2b32wb_fixed:
2421 case ARM::VLD2b8wb_register:
2422 case ARM::VLD2b16wb_register:
2423 case ARM::VLD2b32wb_register:
2424 Inst.addOperand(MCOperand::CreateImm(0));
2425 break;
2426 case ARM::VLD3d8_UPD:
2427 case ARM::VLD3d16_UPD:
2428 case ARM::VLD3d32_UPD:
2429 case ARM::VLD3q8_UPD:
2430 case ARM::VLD3q16_UPD:
2431 case ARM::VLD3q32_UPD:
2432 case ARM::VLD4d8_UPD:
2433 case ARM::VLD4d16_UPD:
2434 case ARM::VLD4d32_UPD:
2435 case ARM::VLD4q8_UPD:
2436 case ARM::VLD4q16_UPD:
2437 case ARM::VLD4q32_UPD:
2438 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2439 return MCDisassembler::Fail;
2440 break;
2441 default:
2442 break;
2443 }
2444
2445 // AddrMode6 Base (register+alignment)
2446 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2447 return MCDisassembler::Fail;
2448
2449 // AddrMode6 Offset (register)
2450 switch (Inst.getOpcode()) {
2451 default:
2452 // The below have been updated to have explicit am6offset split
2453 // between fixed and register offset. For those instructions not
2454 // yet updated, we need to add an additional reg0 operand for the
2455 // fixed variant.
2456 //
2457 // The fixed offset encodes as Rm == 0xd, so we check for that.
2458 if (Rm == 0xd) {
2459 Inst.addOperand(MCOperand::CreateReg(0));
2460 break;
2461 }
2462 // Fall through to handle the register offset variant.
2463 case ARM::VLD1d8wb_fixed:
2464 case ARM::VLD1d16wb_fixed:
2465 case ARM::VLD1d32wb_fixed:
2466 case ARM::VLD1d64wb_fixed:
2467 case ARM::VLD1d8Twb_fixed:
2468 case ARM::VLD1d16Twb_fixed:
2469 case ARM::VLD1d32Twb_fixed:
2470 case ARM::VLD1d64Twb_fixed:
2471 case ARM::VLD1d8Qwb_fixed:
2472 case ARM::VLD1d16Qwb_fixed:
2473 case ARM::VLD1d32Qwb_fixed:
2474 case ARM::VLD1d64Qwb_fixed:
2475 case ARM::VLD1d8wb_register:
2476 case ARM::VLD1d16wb_register:
2477 case ARM::VLD1d32wb_register:
2478 case ARM::VLD1d64wb_register:
2479 case ARM::VLD1q8wb_fixed:
2480 case ARM::VLD1q16wb_fixed:
2481 case ARM::VLD1q32wb_fixed:
2482 case ARM::VLD1q64wb_fixed:
2483 case ARM::VLD1q8wb_register:
2484 case ARM::VLD1q16wb_register:
2485 case ARM::VLD1q32wb_register:
2486 case ARM::VLD1q64wb_register:
2487 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2488 // variant encodes Rm == 0xf. Anything else is a register offset post-
2489 // increment and we need to add the register operand to the instruction.
2490 if (Rm != 0xD && Rm != 0xF &&
2491 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2492 return MCDisassembler::Fail;
2493 break;
2494 case ARM::VLD2d8wb_fixed:
2495 case ARM::VLD2d16wb_fixed:
2496 case ARM::VLD2d32wb_fixed:
2497 case ARM::VLD2b8wb_fixed:
2498 case ARM::VLD2b16wb_fixed:
2499 case ARM::VLD2b32wb_fixed:
2500 case ARM::VLD2q8wb_fixed:
2501 case ARM::VLD2q16wb_fixed:
2502 case ARM::VLD2q32wb_fixed:
2503 break;
2504 }
2505
2506 return S;
2507 }
2508
DecodeVLDST1Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2509 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2510 uint64_t Address, const void *Decoder) {
2511 unsigned type = fieldFromInstruction(Insn, 8, 4);
2512 unsigned align = fieldFromInstruction(Insn, 4, 2);
2513 if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2514 if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2515 if (type == 10 && align == 3) return MCDisassembler::Fail;
2516
2517 unsigned load = fieldFromInstruction(Insn, 21, 1);
2518 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2519 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2520 }
2521
DecodeVLDST2Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2522 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2523 uint64_t Address, const void *Decoder) {
2524 unsigned size = fieldFromInstruction(Insn, 6, 2);
2525 if (size == 3) return MCDisassembler::Fail;
2526
2527 unsigned type = fieldFromInstruction(Insn, 8, 4);
2528 unsigned align = fieldFromInstruction(Insn, 4, 2);
2529 if (type == 8 && align == 3) return MCDisassembler::Fail;
2530 if (type == 9 && align == 3) return MCDisassembler::Fail;
2531
2532 unsigned load = fieldFromInstruction(Insn, 21, 1);
2533 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2534 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2535 }
2536
DecodeVLDST3Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2537 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2538 uint64_t Address, const void *Decoder) {
2539 unsigned size = fieldFromInstruction(Insn, 6, 2);
2540 if (size == 3) return MCDisassembler::Fail;
2541
2542 unsigned align = fieldFromInstruction(Insn, 4, 2);
2543 if (align & 2) return MCDisassembler::Fail;
2544
2545 unsigned load = fieldFromInstruction(Insn, 21, 1);
2546 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2547 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2548 }
2549
DecodeVLDST4Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2550 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2551 uint64_t Address, const void *Decoder) {
2552 unsigned size = fieldFromInstruction(Insn, 6, 2);
2553 if (size == 3) return MCDisassembler::Fail;
2554
2555 unsigned load = fieldFromInstruction(Insn, 21, 1);
2556 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2557 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2558 }
2559
DecodeVSTInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2560 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2561 uint64_t Address, const void *Decoder) {
2562 DecodeStatus S = MCDisassembler::Success;
2563
2564 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2565 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2566 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2567 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2568 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2569 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2570
2571 // Writeback Operand
2572 switch (Inst.getOpcode()) {
2573 case ARM::VST1d8wb_fixed:
2574 case ARM::VST1d16wb_fixed:
2575 case ARM::VST1d32wb_fixed:
2576 case ARM::VST1d64wb_fixed:
2577 case ARM::VST1d8wb_register:
2578 case ARM::VST1d16wb_register:
2579 case ARM::VST1d32wb_register:
2580 case ARM::VST1d64wb_register:
2581 case ARM::VST1q8wb_fixed:
2582 case ARM::VST1q16wb_fixed:
2583 case ARM::VST1q32wb_fixed:
2584 case ARM::VST1q64wb_fixed:
2585 case ARM::VST1q8wb_register:
2586 case ARM::VST1q16wb_register:
2587 case ARM::VST1q32wb_register:
2588 case ARM::VST1q64wb_register:
2589 case ARM::VST1d8Twb_fixed:
2590 case ARM::VST1d16Twb_fixed:
2591 case ARM::VST1d32Twb_fixed:
2592 case ARM::VST1d64Twb_fixed:
2593 case ARM::VST1d8Twb_register:
2594 case ARM::VST1d16Twb_register:
2595 case ARM::VST1d32Twb_register:
2596 case ARM::VST1d64Twb_register:
2597 case ARM::VST1d8Qwb_fixed:
2598 case ARM::VST1d16Qwb_fixed:
2599 case ARM::VST1d32Qwb_fixed:
2600 case ARM::VST1d64Qwb_fixed:
2601 case ARM::VST1d8Qwb_register:
2602 case ARM::VST1d16Qwb_register:
2603 case ARM::VST1d32Qwb_register:
2604 case ARM::VST1d64Qwb_register:
2605 case ARM::VST2d8wb_fixed:
2606 case ARM::VST2d16wb_fixed:
2607 case ARM::VST2d32wb_fixed:
2608 case ARM::VST2d8wb_register:
2609 case ARM::VST2d16wb_register:
2610 case ARM::VST2d32wb_register:
2611 case ARM::VST2q8wb_fixed:
2612 case ARM::VST2q16wb_fixed:
2613 case ARM::VST2q32wb_fixed:
2614 case ARM::VST2q8wb_register:
2615 case ARM::VST2q16wb_register:
2616 case ARM::VST2q32wb_register:
2617 case ARM::VST2b8wb_fixed:
2618 case ARM::VST2b16wb_fixed:
2619 case ARM::VST2b32wb_fixed:
2620 case ARM::VST2b8wb_register:
2621 case ARM::VST2b16wb_register:
2622 case ARM::VST2b32wb_register:
2623 if (Rm == 0xF)
2624 return MCDisassembler::Fail;
2625 Inst.addOperand(MCOperand::CreateImm(0));
2626 break;
2627 case ARM::VST3d8_UPD:
2628 case ARM::VST3d16_UPD:
2629 case ARM::VST3d32_UPD:
2630 case ARM::VST3q8_UPD:
2631 case ARM::VST3q16_UPD:
2632 case ARM::VST3q32_UPD:
2633 case ARM::VST4d8_UPD:
2634 case ARM::VST4d16_UPD:
2635 case ARM::VST4d32_UPD:
2636 case ARM::VST4q8_UPD:
2637 case ARM::VST4q16_UPD:
2638 case ARM::VST4q32_UPD:
2639 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2640 return MCDisassembler::Fail;
2641 break;
2642 default:
2643 break;
2644 }
2645
2646 // AddrMode6 Base (register+alignment)
2647 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2648 return MCDisassembler::Fail;
2649
2650 // AddrMode6 Offset (register)
2651 switch (Inst.getOpcode()) {
2652 default:
2653 if (Rm == 0xD)
2654 Inst.addOperand(MCOperand::CreateReg(0));
2655 else if (Rm != 0xF) {
2656 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2657 return MCDisassembler::Fail;
2658 }
2659 break;
2660 case ARM::VST1d8wb_fixed:
2661 case ARM::VST1d16wb_fixed:
2662 case ARM::VST1d32wb_fixed:
2663 case ARM::VST1d64wb_fixed:
2664 case ARM::VST1q8wb_fixed:
2665 case ARM::VST1q16wb_fixed:
2666 case ARM::VST1q32wb_fixed:
2667 case ARM::VST1q64wb_fixed:
2668 case ARM::VST1d8Twb_fixed:
2669 case ARM::VST1d16Twb_fixed:
2670 case ARM::VST1d32Twb_fixed:
2671 case ARM::VST1d64Twb_fixed:
2672 case ARM::VST1d8Qwb_fixed:
2673 case ARM::VST1d16Qwb_fixed:
2674 case ARM::VST1d32Qwb_fixed:
2675 case ARM::VST1d64Qwb_fixed:
2676 case ARM::VST2d8wb_fixed:
2677 case ARM::VST2d16wb_fixed:
2678 case ARM::VST2d32wb_fixed:
2679 case ARM::VST2q8wb_fixed:
2680 case ARM::VST2q16wb_fixed:
2681 case ARM::VST2q32wb_fixed:
2682 case ARM::VST2b8wb_fixed:
2683 case ARM::VST2b16wb_fixed:
2684 case ARM::VST2b32wb_fixed:
2685 break;
2686 }
2687
2688
2689 // First input register
2690 switch (Inst.getOpcode()) {
2691 case ARM::VST1q16:
2692 case ARM::VST1q32:
2693 case ARM::VST1q64:
2694 case ARM::VST1q8:
2695 case ARM::VST1q16wb_fixed:
2696 case ARM::VST1q16wb_register:
2697 case ARM::VST1q32wb_fixed:
2698 case ARM::VST1q32wb_register:
2699 case ARM::VST1q64wb_fixed:
2700 case ARM::VST1q64wb_register:
2701 case ARM::VST1q8wb_fixed:
2702 case ARM::VST1q8wb_register:
2703 case ARM::VST2d16:
2704 case ARM::VST2d32:
2705 case ARM::VST2d8:
2706 case ARM::VST2d16wb_fixed:
2707 case ARM::VST2d16wb_register:
2708 case ARM::VST2d32wb_fixed:
2709 case ARM::VST2d32wb_register:
2710 case ARM::VST2d8wb_fixed:
2711 case ARM::VST2d8wb_register:
2712 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2713 return MCDisassembler::Fail;
2714 break;
2715 case ARM::VST2b16:
2716 case ARM::VST2b32:
2717 case ARM::VST2b8:
2718 case ARM::VST2b16wb_fixed:
2719 case ARM::VST2b16wb_register:
2720 case ARM::VST2b32wb_fixed:
2721 case ARM::VST2b32wb_register:
2722 case ARM::VST2b8wb_fixed:
2723 case ARM::VST2b8wb_register:
2724 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2725 return MCDisassembler::Fail;
2726 break;
2727 default:
2728 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2729 return MCDisassembler::Fail;
2730 }
2731
2732 // Second input register
2733 switch (Inst.getOpcode()) {
2734 case ARM::VST3d8:
2735 case ARM::VST3d16:
2736 case ARM::VST3d32:
2737 case ARM::VST3d8_UPD:
2738 case ARM::VST3d16_UPD:
2739 case ARM::VST3d32_UPD:
2740 case ARM::VST4d8:
2741 case ARM::VST4d16:
2742 case ARM::VST4d32:
2743 case ARM::VST4d8_UPD:
2744 case ARM::VST4d16_UPD:
2745 case ARM::VST4d32_UPD:
2746 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2747 return MCDisassembler::Fail;
2748 break;
2749 case ARM::VST3q8:
2750 case ARM::VST3q16:
2751 case ARM::VST3q32:
2752 case ARM::VST3q8_UPD:
2753 case ARM::VST3q16_UPD:
2754 case ARM::VST3q32_UPD:
2755 case ARM::VST4q8:
2756 case ARM::VST4q16:
2757 case ARM::VST4q32:
2758 case ARM::VST4q8_UPD:
2759 case ARM::VST4q16_UPD:
2760 case ARM::VST4q32_UPD:
2761 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2762 return MCDisassembler::Fail;
2763 break;
2764 default:
2765 break;
2766 }
2767
2768 // Third input register
2769 switch (Inst.getOpcode()) {
2770 case ARM::VST3d8:
2771 case ARM::VST3d16:
2772 case ARM::VST3d32:
2773 case ARM::VST3d8_UPD:
2774 case ARM::VST3d16_UPD:
2775 case ARM::VST3d32_UPD:
2776 case ARM::VST4d8:
2777 case ARM::VST4d16:
2778 case ARM::VST4d32:
2779 case ARM::VST4d8_UPD:
2780 case ARM::VST4d16_UPD:
2781 case ARM::VST4d32_UPD:
2782 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2783 return MCDisassembler::Fail;
2784 break;
2785 case ARM::VST3q8:
2786 case ARM::VST3q16:
2787 case ARM::VST3q32:
2788 case ARM::VST3q8_UPD:
2789 case ARM::VST3q16_UPD:
2790 case ARM::VST3q32_UPD:
2791 case ARM::VST4q8:
2792 case ARM::VST4q16:
2793 case ARM::VST4q32:
2794 case ARM::VST4q8_UPD:
2795 case ARM::VST4q16_UPD:
2796 case ARM::VST4q32_UPD:
2797 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2798 return MCDisassembler::Fail;
2799 break;
2800 default:
2801 break;
2802 }
2803
2804 // Fourth input register
2805 switch (Inst.getOpcode()) {
2806 case ARM::VST4d8:
2807 case ARM::VST4d16:
2808 case ARM::VST4d32:
2809 case ARM::VST4d8_UPD:
2810 case ARM::VST4d16_UPD:
2811 case ARM::VST4d32_UPD:
2812 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2813 return MCDisassembler::Fail;
2814 break;
2815 case ARM::VST4q8:
2816 case ARM::VST4q16:
2817 case ARM::VST4q32:
2818 case ARM::VST4q8_UPD:
2819 case ARM::VST4q16_UPD:
2820 case ARM::VST4q32_UPD:
2821 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2822 return MCDisassembler::Fail;
2823 break;
2824 default:
2825 break;
2826 }
2827
2828 return S;
2829 }
2830
DecodeVLD1DupInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2831 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2832 uint64_t Address, const void *Decoder) {
2833 DecodeStatus S = MCDisassembler::Success;
2834
2835 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2836 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2837 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2838 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2839 unsigned align = fieldFromInstruction(Insn, 4, 1);
2840 unsigned size = fieldFromInstruction(Insn, 6, 2);
2841
2842 if (size == 0 && align == 1)
2843 return MCDisassembler::Fail;
2844 align *= (1 << size);
2845
2846 switch (Inst.getOpcode()) {
2847 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2848 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2849 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2850 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2851 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2852 return MCDisassembler::Fail;
2853 break;
2854 default:
2855 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2856 return MCDisassembler::Fail;
2857 break;
2858 }
2859 if (Rm != 0xF) {
2860 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2861 return MCDisassembler::Fail;
2862 }
2863
2864 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2865 return MCDisassembler::Fail;
2866 Inst.addOperand(MCOperand::CreateImm(align));
2867
2868 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2869 // variant encodes Rm == 0xf. Anything else is a register offset post-
2870 // increment and we need to add the register operand to the instruction.
2871 if (Rm != 0xD && Rm != 0xF &&
2872 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2873 return MCDisassembler::Fail;
2874
2875 return S;
2876 }
2877
DecodeVLD2DupInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2878 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2879 uint64_t Address, const void *Decoder) {
2880 DecodeStatus S = MCDisassembler::Success;
2881
2882 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2883 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2884 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2885 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2886 unsigned align = fieldFromInstruction(Insn, 4, 1);
2887 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2888 align *= 2*size;
2889
2890 switch (Inst.getOpcode()) {
2891 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2892 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2893 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2894 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2895 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2896 return MCDisassembler::Fail;
2897 break;
2898 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2899 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2900 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2901 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2902 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2903 return MCDisassembler::Fail;
2904 break;
2905 default:
2906 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2907 return MCDisassembler::Fail;
2908 break;
2909 }
2910
2911 if (Rm != 0xF)
2912 Inst.addOperand(MCOperand::CreateImm(0));
2913
2914 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2915 return MCDisassembler::Fail;
2916 Inst.addOperand(MCOperand::CreateImm(align));
2917
2918 if (Rm != 0xD && Rm != 0xF) {
2919 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2920 return MCDisassembler::Fail;
2921 }
2922
2923 return S;
2924 }
2925
DecodeVLD3DupInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2926 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
2927 uint64_t Address, const void *Decoder) {
2928 DecodeStatus S = MCDisassembler::Success;
2929
2930 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2931 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2932 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2933 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2934 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2935
2936 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2937 return MCDisassembler::Fail;
2938 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2939 return MCDisassembler::Fail;
2940 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2941 return MCDisassembler::Fail;
2942 if (Rm != 0xF) {
2943 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2944 return MCDisassembler::Fail;
2945 }
2946
2947 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2948 return MCDisassembler::Fail;
2949 Inst.addOperand(MCOperand::CreateImm(0));
2950
2951 if (Rm == 0xD)
2952 Inst.addOperand(MCOperand::CreateReg(0));
2953 else if (Rm != 0xF) {
2954 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2955 return MCDisassembler::Fail;
2956 }
2957
2958 return S;
2959 }
2960
DecodeVLD4DupInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)2961 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
2962 uint64_t Address, const void *Decoder) {
2963 DecodeStatus S = MCDisassembler::Success;
2964
2965 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2966 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2967 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2968 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2969 unsigned size = fieldFromInstruction(Insn, 6, 2);
2970 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2971 unsigned align = fieldFromInstruction(Insn, 4, 1);
2972
2973 if (size == 0x3) {
2974 if (align == 0)
2975 return MCDisassembler::Fail;
2976 size = 4;
2977 align = 16;
2978 } else {
2979 if (size == 2) {
2980 size = 1 << size;
2981 align *= 8;
2982 } else {
2983 size = 1 << size;
2984 align *= 4*size;
2985 }
2986 }
2987
2988 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2989 return MCDisassembler::Fail;
2990 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2991 return MCDisassembler::Fail;
2992 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2993 return MCDisassembler::Fail;
2994 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2995 return MCDisassembler::Fail;
2996 if (Rm != 0xF) {
2997 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2998 return MCDisassembler::Fail;
2999 }
3000
3001 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3002 return MCDisassembler::Fail;
3003 Inst.addOperand(MCOperand::CreateImm(align));
3004
3005 if (Rm == 0xD)
3006 Inst.addOperand(MCOperand::CreateReg(0));
3007 else if (Rm != 0xF) {
3008 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3009 return MCDisassembler::Fail;
3010 }
3011
3012 return S;
3013 }
3014
3015 static DecodeStatus
DecodeNEONModImmInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3016 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
3017 uint64_t Address, const void *Decoder) {
3018 DecodeStatus S = MCDisassembler::Success;
3019
3020 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3021 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3022 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3023 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3024 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3025 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3026 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3027 unsigned Q = fieldFromInstruction(Insn, 6, 1);
3028
3029 if (Q) {
3030 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3031 return MCDisassembler::Fail;
3032 } else {
3033 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3034 return MCDisassembler::Fail;
3035 }
3036
3037 Inst.addOperand(MCOperand::CreateImm(imm));
3038
3039 switch (Inst.getOpcode()) {
3040 case ARM::VORRiv4i16:
3041 case ARM::VORRiv2i32:
3042 case ARM::VBICiv4i16:
3043 case ARM::VBICiv2i32:
3044 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3045 return MCDisassembler::Fail;
3046 break;
3047 case ARM::VORRiv8i16:
3048 case ARM::VORRiv4i32:
3049 case ARM::VBICiv8i16:
3050 case ARM::VBICiv4i32:
3051 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3052 return MCDisassembler::Fail;
3053 break;
3054 default:
3055 break;
3056 }
3057
3058 return S;
3059 }
3060
DecodeVSHLMaxInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3061 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3062 uint64_t Address, const void *Decoder) {
3063 DecodeStatus S = MCDisassembler::Success;
3064
3065 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3066 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3067 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3068 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3069 unsigned size = fieldFromInstruction(Insn, 18, 2);
3070
3071 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3072 return MCDisassembler::Fail;
3073 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3074 return MCDisassembler::Fail;
3075 Inst.addOperand(MCOperand::CreateImm(8 << size));
3076
3077 return S;
3078 }
3079
DecodeShiftRight8Imm(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3080 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3081 uint64_t Address, const void *Decoder) {
3082 Inst.addOperand(MCOperand::CreateImm(8 - Val));
3083 return MCDisassembler::Success;
3084 }
3085
DecodeShiftRight16Imm(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3086 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3087 uint64_t Address, const void *Decoder) {
3088 Inst.addOperand(MCOperand::CreateImm(16 - Val));
3089 return MCDisassembler::Success;
3090 }
3091
DecodeShiftRight32Imm(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3092 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3093 uint64_t Address, const void *Decoder) {
3094 Inst.addOperand(MCOperand::CreateImm(32 - Val));
3095 return MCDisassembler::Success;
3096 }
3097
DecodeShiftRight64Imm(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3098 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3099 uint64_t Address, const void *Decoder) {
3100 Inst.addOperand(MCOperand::CreateImm(64 - Val));
3101 return MCDisassembler::Success;
3102 }
3103
DecodeTBLInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3104 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3105 uint64_t Address, const void *Decoder) {
3106 DecodeStatus S = MCDisassembler::Success;
3107
3108 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3109 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3110 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3111 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3112 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3113 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3114 unsigned op = fieldFromInstruction(Insn, 6, 1);
3115
3116 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3117 return MCDisassembler::Fail;
3118 if (op) {
3119 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3120 return MCDisassembler::Fail; // Writeback
3121 }
3122
3123 switch (Inst.getOpcode()) {
3124 case ARM::VTBL2:
3125 case ARM::VTBX2:
3126 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3127 return MCDisassembler::Fail;
3128 break;
3129 default:
3130 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3131 return MCDisassembler::Fail;
3132 }
3133
3134 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3135 return MCDisassembler::Fail;
3136
3137 return S;
3138 }
3139
DecodeThumbAddSpecialReg(MCInst & Inst,uint16_t Insn,uint64_t Address,const void * Decoder)3140 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3141 uint64_t Address, const void *Decoder) {
3142 DecodeStatus S = MCDisassembler::Success;
3143
3144 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3145 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3146
3147 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3148 return MCDisassembler::Fail;
3149
3150 switch(Inst.getOpcode()) {
3151 default:
3152 return MCDisassembler::Fail;
3153 case ARM::tADR:
3154 break; // tADR does not explicitly represent the PC as an operand.
3155 case ARM::tADDrSPi:
3156 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3157 break;
3158 }
3159
3160 Inst.addOperand(MCOperand::CreateImm(imm));
3161 return S;
3162 }
3163
DecodeThumbBROperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3164 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3165 uint64_t Address, const void *Decoder) {
3166 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3167 true, 2, Inst, Decoder))
3168 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
3169 return MCDisassembler::Success;
3170 }
3171
DecodeT2BROperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3172 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3173 uint64_t Address, const void *Decoder) {
3174 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3175 true, 4, Inst, Decoder))
3176 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
3177 return MCDisassembler::Success;
3178 }
3179
DecodeThumbCmpBROperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3180 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3181 uint64_t Address, const void *Decoder) {
3182 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3183 true, 2, Inst, Decoder))
3184 Inst.addOperand(MCOperand::CreateImm(Val << 1));
3185 return MCDisassembler::Success;
3186 }
3187
DecodeThumbAddrModeRR(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3188 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3189 uint64_t Address, const void *Decoder) {
3190 DecodeStatus S = MCDisassembler::Success;
3191
3192 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3193 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3194
3195 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3196 return MCDisassembler::Fail;
3197 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3198 return MCDisassembler::Fail;
3199
3200 return S;
3201 }
3202
DecodeThumbAddrModeIS(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3203 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3204 uint64_t Address, const void *Decoder) {
3205 DecodeStatus S = MCDisassembler::Success;
3206
3207 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3208 unsigned imm = fieldFromInstruction(Val, 3, 5);
3209
3210 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3211 return MCDisassembler::Fail;
3212 Inst.addOperand(MCOperand::CreateImm(imm));
3213
3214 return S;
3215 }
3216
DecodeThumbAddrModePC(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3217 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3218 uint64_t Address, const void *Decoder) {
3219 unsigned imm = Val << 2;
3220
3221 Inst.addOperand(MCOperand::CreateImm(imm));
3222 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3223
3224 return MCDisassembler::Success;
3225 }
3226
DecodeThumbAddrModeSP(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3227 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3228 uint64_t Address, const void *Decoder) {
3229 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3230 Inst.addOperand(MCOperand::CreateImm(Val));
3231
3232 return MCDisassembler::Success;
3233 }
3234
DecodeT2AddrModeSOReg(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3235 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3236 uint64_t Address, const void *Decoder) {
3237 DecodeStatus S = MCDisassembler::Success;
3238
3239 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3240 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3241 unsigned imm = fieldFromInstruction(Val, 0, 2);
3242
3243 // Thumb stores cannot use PC as dest register.
3244 switch (Inst.getOpcode()) {
3245 case ARM::t2STRHs:
3246 case ARM::t2STRBs:
3247 case ARM::t2STRs:
3248 if (Rn == 15)
3249 return MCDisassembler::Fail;
3250 default:
3251 break;
3252 }
3253
3254 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3255 return MCDisassembler::Fail;
3256 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3257 return MCDisassembler::Fail;
3258 Inst.addOperand(MCOperand::CreateImm(imm));
3259
3260 return S;
3261 }
3262
DecodeT2LoadShift(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3263 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3264 uint64_t Address, const void *Decoder) {
3265 DecodeStatus S = MCDisassembler::Success;
3266
3267 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3268 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3269
3270 if (Rn == 15) {
3271 switch (Inst.getOpcode()) {
3272 case ARM::t2LDRBs:
3273 Inst.setOpcode(ARM::t2LDRBpci);
3274 break;
3275 case ARM::t2LDRHs:
3276 Inst.setOpcode(ARM::t2LDRHpci);
3277 break;
3278 case ARM::t2LDRSHs:
3279 Inst.setOpcode(ARM::t2LDRSHpci);
3280 break;
3281 case ARM::t2LDRSBs:
3282 Inst.setOpcode(ARM::t2LDRSBpci);
3283 break;
3284 case ARM::t2LDRs:
3285 Inst.setOpcode(ARM::t2LDRpci);
3286 break;
3287 case ARM::t2PLDs:
3288 Inst.setOpcode(ARM::t2PLDpci);
3289 break;
3290 case ARM::t2PLIs:
3291 Inst.setOpcode(ARM::t2PLIpci);
3292 break;
3293 default:
3294 return MCDisassembler::Fail;
3295 }
3296
3297 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3298 }
3299
3300 if (Rt == 15) {
3301 switch (Inst.getOpcode()) {
3302 case ARM::t2LDRSHs:
3303 return MCDisassembler::Fail;
3304 case ARM::t2LDRHs:
3305 // FIXME: this instruction is only available with MP extensions,
3306 // this should be checked first but we don't have access to the
3307 // feature bits here.
3308 Inst.setOpcode(ARM::t2PLDWs);
3309 break;
3310 default:
3311 break;
3312 }
3313 }
3314
3315 switch (Inst.getOpcode()) {
3316 case ARM::t2PLDs:
3317 case ARM::t2PLDWs:
3318 case ARM::t2PLIs:
3319 break;
3320 default:
3321 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3322 return MCDisassembler::Fail;
3323 }
3324
3325 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3326 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3327 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3328 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3329 return MCDisassembler::Fail;
3330
3331 return S;
3332 }
3333
DecodeT2LoadImm8(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3334 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3335 uint64_t Address, const void* Decoder) {
3336 DecodeStatus S = MCDisassembler::Success;
3337
3338 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3339 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3340 unsigned U = fieldFromInstruction(Insn, 9, 1);
3341 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3342 imm |= (U << 8);
3343 imm |= (Rn << 9);
3344
3345 if (Rn == 15) {
3346 switch (Inst.getOpcode()) {
3347 case ARM::t2LDRi8:
3348 Inst.setOpcode(ARM::t2LDRpci);
3349 break;
3350 case ARM::t2LDRBi8:
3351 Inst.setOpcode(ARM::t2LDRBpci);
3352 break;
3353 case ARM::t2LDRSBi8:
3354 Inst.setOpcode(ARM::t2LDRSBpci);
3355 break;
3356 case ARM::t2LDRHi8:
3357 Inst.setOpcode(ARM::t2LDRHpci);
3358 break;
3359 case ARM::t2LDRSHi8:
3360 Inst.setOpcode(ARM::t2LDRSHpci);
3361 break;
3362 case ARM::t2PLDi8:
3363 Inst.setOpcode(ARM::t2PLDpci);
3364 break;
3365 case ARM::t2PLIi8:
3366 Inst.setOpcode(ARM::t2PLIpci);
3367 break;
3368 default:
3369 return MCDisassembler::Fail;
3370 }
3371 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3372 }
3373
3374 if (Rt == 15) {
3375 switch (Inst.getOpcode()) {
3376 case ARM::t2LDRSHi8:
3377 return MCDisassembler::Fail;
3378 default:
3379 break;
3380 }
3381 }
3382
3383 switch (Inst.getOpcode()) {
3384 case ARM::t2PLDi8:
3385 case ARM::t2PLIi8:
3386 case ARM::t2PLDWi8:
3387 break;
3388 default:
3389 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3390 return MCDisassembler::Fail;
3391 }
3392
3393 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3394 return MCDisassembler::Fail;
3395 return S;
3396 }
3397
DecodeT2LoadImm12(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3398 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3399 uint64_t Address, const void* Decoder) {
3400 DecodeStatus S = MCDisassembler::Success;
3401
3402 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3403 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3404 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3405 imm |= (Rn << 13);
3406
3407 if (Rn == 15) {
3408 switch (Inst.getOpcode()) {
3409 case ARM::t2LDRi12:
3410 Inst.setOpcode(ARM::t2LDRpci);
3411 break;
3412 case ARM::t2LDRHi12:
3413 Inst.setOpcode(ARM::t2LDRHpci);
3414 break;
3415 case ARM::t2LDRSHi12:
3416 Inst.setOpcode(ARM::t2LDRSHpci);
3417 break;
3418 case ARM::t2LDRBi12:
3419 Inst.setOpcode(ARM::t2LDRBpci);
3420 break;
3421 case ARM::t2LDRSBi12:
3422 Inst.setOpcode(ARM::t2LDRSBpci);
3423 break;
3424 case ARM::t2PLDi12:
3425 Inst.setOpcode(ARM::t2PLDpci);
3426 break;
3427 case ARM::t2PLIi12:
3428 Inst.setOpcode(ARM::t2PLIpci);
3429 break;
3430 default:
3431 return MCDisassembler::Fail;
3432 }
3433 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3434 }
3435
3436 if (Rt == 15) {
3437 switch (Inst.getOpcode()) {
3438 case ARM::t2LDRSHi12:
3439 return MCDisassembler::Fail;
3440 case ARM::t2LDRHi12:
3441 Inst.setOpcode(ARM::t2PLDi12);
3442 break;
3443 default:
3444 break;
3445 }
3446 }
3447
3448 switch (Inst.getOpcode()) {
3449 case ARM::t2PLDi12:
3450 case ARM::t2PLDWi12:
3451 case ARM::t2PLIi12:
3452 break;
3453 default:
3454 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3455 return MCDisassembler::Fail;
3456 }
3457
3458 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3459 return MCDisassembler::Fail;
3460 return S;
3461 }
3462
DecodeT2LoadT(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3463 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
3464 uint64_t Address, const void* Decoder) {
3465 DecodeStatus S = MCDisassembler::Success;
3466
3467 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3468 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3469 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3470 imm |= (Rn << 9);
3471
3472 if (Rn == 15) {
3473 switch (Inst.getOpcode()) {
3474 case ARM::t2LDRT:
3475 Inst.setOpcode(ARM::t2LDRpci);
3476 break;
3477 case ARM::t2LDRBT:
3478 Inst.setOpcode(ARM::t2LDRBpci);
3479 break;
3480 case ARM::t2LDRHT:
3481 Inst.setOpcode(ARM::t2LDRHpci);
3482 break;
3483 case ARM::t2LDRSBT:
3484 Inst.setOpcode(ARM::t2LDRSBpci);
3485 break;
3486 case ARM::t2LDRSHT:
3487 Inst.setOpcode(ARM::t2LDRSHpci);
3488 break;
3489 default:
3490 return MCDisassembler::Fail;
3491 }
3492 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3493 }
3494
3495 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3496 return MCDisassembler::Fail;
3497 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3498 return MCDisassembler::Fail;
3499 return S;
3500 }
3501
DecodeT2LoadLabel(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3502 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
3503 uint64_t Address, const void* Decoder) {
3504 DecodeStatus S = MCDisassembler::Success;
3505
3506 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3507 unsigned U = fieldFromInstruction(Insn, 23, 1);
3508 int imm = fieldFromInstruction(Insn, 0, 12);
3509
3510 if (Rt == 15) {
3511 switch (Inst.getOpcode()) {
3512 case ARM::t2LDRBpci:
3513 case ARM::t2LDRHpci:
3514 Inst.setOpcode(ARM::t2PLDpci);
3515 break;
3516 case ARM::t2LDRSBpci:
3517 Inst.setOpcode(ARM::t2PLIpci);
3518 break;
3519 case ARM::t2LDRSHpci:
3520 return MCDisassembler::Fail;
3521 default:
3522 break;
3523 }
3524 }
3525
3526 switch(Inst.getOpcode()) {
3527 case ARM::t2PLDpci:
3528 case ARM::t2PLIpci:
3529 break;
3530 default:
3531 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3532 return MCDisassembler::Fail;
3533 }
3534
3535 if (!U) {
3536 // Special case for #-0.
3537 if (imm == 0)
3538 imm = INT32_MIN;
3539 else
3540 imm = -imm;
3541 }
3542 Inst.addOperand(MCOperand::CreateImm(imm));
3543
3544 return S;
3545 }
3546
DecodeT2Imm8S4(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3547 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3548 uint64_t Address, const void *Decoder) {
3549 if (Val == 0)
3550 Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
3551 else {
3552 int imm = Val & 0xFF;
3553
3554 if (!(Val & 0x100)) imm *= -1;
3555 Inst.addOperand(MCOperand::CreateImm(imm * 4));
3556 }
3557
3558 return MCDisassembler::Success;
3559 }
3560
DecodeT2AddrModeImm8s4(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3561 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3562 uint64_t Address, const void *Decoder) {
3563 DecodeStatus S = MCDisassembler::Success;
3564
3565 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3566 unsigned imm = fieldFromInstruction(Val, 0, 9);
3567
3568 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3569 return MCDisassembler::Fail;
3570 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3571 return MCDisassembler::Fail;
3572
3573 return S;
3574 }
3575
DecodeT2AddrModeImm0_1020s4(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3576 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
3577 uint64_t Address, const void *Decoder) {
3578 DecodeStatus S = MCDisassembler::Success;
3579
3580 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3581 unsigned imm = fieldFromInstruction(Val, 0, 8);
3582
3583 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3584 return MCDisassembler::Fail;
3585
3586 Inst.addOperand(MCOperand::CreateImm(imm));
3587
3588 return S;
3589 }
3590
DecodeT2Imm8(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3591 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3592 uint64_t Address, const void *Decoder) {
3593 int imm = Val & 0xFF;
3594 if (Val == 0)
3595 imm = INT32_MIN;
3596 else if (!(Val & 0x100))
3597 imm *= -1;
3598 Inst.addOperand(MCOperand::CreateImm(imm));
3599
3600 return MCDisassembler::Success;
3601 }
3602
3603
DecodeT2AddrModeImm8(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3604 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3605 uint64_t Address, const void *Decoder) {
3606 DecodeStatus S = MCDisassembler::Success;
3607
3608 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3609 unsigned imm = fieldFromInstruction(Val, 0, 9);
3610
3611 // Thumb stores cannot use PC as dest register.
3612 switch (Inst.getOpcode()) {
3613 case ARM::t2STRT:
3614 case ARM::t2STRBT:
3615 case ARM::t2STRHT:
3616 case ARM::t2STRi8:
3617 case ARM::t2STRHi8:
3618 case ARM::t2STRBi8:
3619 if (Rn == 15)
3620 return MCDisassembler::Fail;
3621 break;
3622 default:
3623 break;
3624 }
3625
3626 // Some instructions always use an additive offset.
3627 switch (Inst.getOpcode()) {
3628 case ARM::t2LDRT:
3629 case ARM::t2LDRBT:
3630 case ARM::t2LDRHT:
3631 case ARM::t2LDRSBT:
3632 case ARM::t2LDRSHT:
3633 case ARM::t2STRT:
3634 case ARM::t2STRBT:
3635 case ARM::t2STRHT:
3636 imm |= 0x100;
3637 break;
3638 default:
3639 break;
3640 }
3641
3642 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3643 return MCDisassembler::Fail;
3644 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3645 return MCDisassembler::Fail;
3646
3647 return S;
3648 }
3649
DecodeT2LdStPre(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3650 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3651 uint64_t Address, const void *Decoder) {
3652 DecodeStatus S = MCDisassembler::Success;
3653
3654 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3655 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3656 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3657 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3658 addr |= Rn << 9;
3659 unsigned load = fieldFromInstruction(Insn, 20, 1);
3660
3661 if (Rn == 15) {
3662 switch (Inst.getOpcode()) {
3663 case ARM::t2LDR_PRE:
3664 case ARM::t2LDR_POST:
3665 Inst.setOpcode(ARM::t2LDRpci);
3666 break;
3667 case ARM::t2LDRB_PRE:
3668 case ARM::t2LDRB_POST:
3669 Inst.setOpcode(ARM::t2LDRBpci);
3670 break;
3671 case ARM::t2LDRH_PRE:
3672 case ARM::t2LDRH_POST:
3673 Inst.setOpcode(ARM::t2LDRHpci);
3674 break;
3675 case ARM::t2LDRSB_PRE:
3676 case ARM::t2LDRSB_POST:
3677 if (Rt == 15)
3678 Inst.setOpcode(ARM::t2PLIpci);
3679 else
3680 Inst.setOpcode(ARM::t2LDRSBpci);
3681 break;
3682 case ARM::t2LDRSH_PRE:
3683 case ARM::t2LDRSH_POST:
3684 Inst.setOpcode(ARM::t2LDRSHpci);
3685 break;
3686 default:
3687 return MCDisassembler::Fail;
3688 }
3689 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3690 }
3691
3692 if (!load) {
3693 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3694 return MCDisassembler::Fail;
3695 }
3696
3697 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3698 return MCDisassembler::Fail;
3699
3700 if (load) {
3701 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3702 return MCDisassembler::Fail;
3703 }
3704
3705 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3706 return MCDisassembler::Fail;
3707
3708 return S;
3709 }
3710
DecodeT2AddrModeImm12(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3711 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3712 uint64_t Address, const void *Decoder) {
3713 DecodeStatus S = MCDisassembler::Success;
3714
3715 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3716 unsigned imm = fieldFromInstruction(Val, 0, 12);
3717
3718 // Thumb stores cannot use PC as dest register.
3719 switch (Inst.getOpcode()) {
3720 case ARM::t2STRi12:
3721 case ARM::t2STRBi12:
3722 case ARM::t2STRHi12:
3723 if (Rn == 15)
3724 return MCDisassembler::Fail;
3725 default:
3726 break;
3727 }
3728
3729 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3730 return MCDisassembler::Fail;
3731 Inst.addOperand(MCOperand::CreateImm(imm));
3732
3733 return S;
3734 }
3735
3736
DecodeThumbAddSPImm(MCInst & Inst,uint16_t Insn,uint64_t Address,const void * Decoder)3737 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3738 uint64_t Address, const void *Decoder) {
3739 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3740
3741 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3742 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3743 Inst.addOperand(MCOperand::CreateImm(imm));
3744
3745 return MCDisassembler::Success;
3746 }
3747
DecodeThumbAddSPReg(MCInst & Inst,uint16_t Insn,uint64_t Address,const void * Decoder)3748 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3749 uint64_t Address, const void *Decoder) {
3750 DecodeStatus S = MCDisassembler::Success;
3751
3752 if (Inst.getOpcode() == ARM::tADDrSP) {
3753 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3754 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3755
3756 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3757 return MCDisassembler::Fail;
3758 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3759 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3760 return MCDisassembler::Fail;
3761 } else if (Inst.getOpcode() == ARM::tADDspr) {
3762 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3763
3764 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3765 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3766 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3767 return MCDisassembler::Fail;
3768 }
3769
3770 return S;
3771 }
3772
DecodeThumbCPS(MCInst & Inst,uint16_t Insn,uint64_t Address,const void * Decoder)3773 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3774 uint64_t Address, const void *Decoder) {
3775 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3776 unsigned flags = fieldFromInstruction(Insn, 0, 3);
3777
3778 Inst.addOperand(MCOperand::CreateImm(imod));
3779 Inst.addOperand(MCOperand::CreateImm(flags));
3780
3781 return MCDisassembler::Success;
3782 }
3783
DecodePostIdxReg(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3784 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3785 uint64_t Address, const void *Decoder) {
3786 DecodeStatus S = MCDisassembler::Success;
3787 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3788 unsigned add = fieldFromInstruction(Insn, 4, 1);
3789
3790 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3791 return MCDisassembler::Fail;
3792 Inst.addOperand(MCOperand::CreateImm(add));
3793
3794 return S;
3795 }
3796
DecodeThumbBLXOffset(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3797 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3798 uint64_t Address, const void *Decoder) {
3799 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3800 // Note only one trailing zero not two. Also the J1 and J2 values are from
3801 // the encoded instruction. So here change to I1 and I2 values via:
3802 // I1 = NOT(J1 EOR S);
3803 // I2 = NOT(J2 EOR S);
3804 // and build the imm32 with two trailing zeros as documented:
3805 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3806 unsigned S = (Val >> 23) & 1;
3807 unsigned J1 = (Val >> 22) & 1;
3808 unsigned J2 = (Val >> 21) & 1;
3809 unsigned I1 = !(J1 ^ S);
3810 unsigned I2 = !(J2 ^ S);
3811 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3812 int imm32 = SignExtend32<25>(tmp << 1);
3813
3814 if (!tryAddingSymbolicOperand(Address,
3815 (Address & ~2u) + imm32 + 4,
3816 true, 4, Inst, Decoder))
3817 Inst.addOperand(MCOperand::CreateImm(imm32));
3818 return MCDisassembler::Success;
3819 }
3820
DecodeCoprocessor(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3821 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3822 uint64_t Address, const void *Decoder) {
3823 if (Val == 0xA || Val == 0xB)
3824 return MCDisassembler::Fail;
3825
3826 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3827 .getFeatureBits();
3828 if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15))
3829 return MCDisassembler::Fail;
3830
3831 Inst.addOperand(MCOperand::CreateImm(Val));
3832 return MCDisassembler::Success;
3833 }
3834
3835 static DecodeStatus
DecodeThumbTableBranch(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3836 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3837 uint64_t Address, const void *Decoder) {
3838 DecodeStatus S = MCDisassembler::Success;
3839
3840 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3841 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3842
3843 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3844 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3845 return MCDisassembler::Fail;
3846 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3847 return MCDisassembler::Fail;
3848 return S;
3849 }
3850
3851 static DecodeStatus
DecodeThumb2BCCInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3852 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
3853 uint64_t Address, const void *Decoder) {
3854 DecodeStatus S = MCDisassembler::Success;
3855
3856 unsigned pred = fieldFromInstruction(Insn, 22, 4);
3857 if (pred == 0xE || pred == 0xF) {
3858 unsigned opc = fieldFromInstruction(Insn, 4, 28);
3859 switch (opc) {
3860 default:
3861 return MCDisassembler::Fail;
3862 case 0xf3bf8f4:
3863 Inst.setOpcode(ARM::t2DSB);
3864 break;
3865 case 0xf3bf8f5:
3866 Inst.setOpcode(ARM::t2DMB);
3867 break;
3868 case 0xf3bf8f6:
3869 Inst.setOpcode(ARM::t2ISB);
3870 break;
3871 }
3872
3873 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3874 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3875 }
3876
3877 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3878 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3879 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3880 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3881 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
3882
3883 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3884 return MCDisassembler::Fail;
3885 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3886 return MCDisassembler::Fail;
3887
3888 return S;
3889 }
3890
3891 // Decode a shifted immediate operand. These basically consist
3892 // of an 8-bit value, and a 4-bit directive that specifies either
3893 // a splat operation or a rotation.
DecodeT2SOImm(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3894 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
3895 uint64_t Address, const void *Decoder) {
3896 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
3897 if (ctrl == 0) {
3898 unsigned byte = fieldFromInstruction(Val, 8, 2);
3899 unsigned imm = fieldFromInstruction(Val, 0, 8);
3900 switch (byte) {
3901 case 0:
3902 Inst.addOperand(MCOperand::CreateImm(imm));
3903 break;
3904 case 1:
3905 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3906 break;
3907 case 2:
3908 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3909 break;
3910 case 3:
3911 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3912 (imm << 8) | imm));
3913 break;
3914 }
3915 } else {
3916 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
3917 unsigned rot = fieldFromInstruction(Val, 7, 5);
3918 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3919 Inst.addOperand(MCOperand::CreateImm(imm));
3920 }
3921
3922 return MCDisassembler::Success;
3923 }
3924
3925 static DecodeStatus
DecodeThumbBCCTargetOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3926 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
3927 uint64_t Address, const void *Decoder){
3928 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
3929 true, 2, Inst, Decoder))
3930 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
3931 return MCDisassembler::Success;
3932 }
3933
DecodeThumbBLTargetOperand(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3934 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
3935 uint64_t Address, const void *Decoder){
3936 // Val is passed in as S:J1:J2:imm10:imm11
3937 // Note no trailing zero after imm11. Also the J1 and J2 values are from
3938 // the encoded instruction. So here change to I1 and I2 values via:
3939 // I1 = NOT(J1 EOR S);
3940 // I2 = NOT(J2 EOR S);
3941 // and build the imm32 with one trailing zero as documented:
3942 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
3943 unsigned S = (Val >> 23) & 1;
3944 unsigned J1 = (Val >> 22) & 1;
3945 unsigned J2 = (Val >> 21) & 1;
3946 unsigned I1 = !(J1 ^ S);
3947 unsigned I2 = !(J2 ^ S);
3948 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3949 int imm32 = SignExtend32<25>(tmp << 1);
3950
3951 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
3952 true, 4, Inst, Decoder))
3953 Inst.addOperand(MCOperand::CreateImm(imm32));
3954 return MCDisassembler::Success;
3955 }
3956
DecodeMemBarrierOption(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3957 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
3958 uint64_t Address, const void *Decoder) {
3959 if (Val & ~0xf)
3960 return MCDisassembler::Fail;
3961
3962 Inst.addOperand(MCOperand::CreateImm(Val));
3963 return MCDisassembler::Success;
3964 }
3965
DecodeInstSyncBarrierOption(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3966 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
3967 uint64_t Address, const void *Decoder) {
3968 if (Val & ~0xf)
3969 return MCDisassembler::Fail;
3970
3971 Inst.addOperand(MCOperand::CreateImm(Val));
3972 return MCDisassembler::Success;
3973 }
3974
DecodeMSRMask(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)3975 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
3976 uint64_t Address, const void *Decoder) {
3977 if (!Val) return MCDisassembler::Fail;
3978 Inst.addOperand(MCOperand::CreateImm(Val));
3979 return MCDisassembler::Success;
3980 }
3981
DecodeDoubleRegLoad(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)3982 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
3983 uint64_t Address, const void *Decoder) {
3984 DecodeStatus S = MCDisassembler::Success;
3985
3986 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3987 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3988 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3989
3990 if (Rn == 0xF)
3991 S = MCDisassembler::SoftFail;
3992
3993 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
3994 return MCDisassembler::Fail;
3995 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3996 return MCDisassembler::Fail;
3997 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3998 return MCDisassembler::Fail;
3999
4000 return S;
4001 }
4002
DecodeDoubleRegStore(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4003 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4004 uint64_t Address, const void *Decoder){
4005 DecodeStatus S = MCDisassembler::Success;
4006
4007 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4008 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4009 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4010 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4011
4012 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4013 return MCDisassembler::Fail;
4014
4015 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4016 S = MCDisassembler::SoftFail;
4017
4018 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4019 return MCDisassembler::Fail;
4020 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4021 return MCDisassembler::Fail;
4022 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4023 return MCDisassembler::Fail;
4024
4025 return S;
4026 }
4027
DecodeLDRPreImm(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4028 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4029 uint64_t Address, const void *Decoder) {
4030 DecodeStatus S = MCDisassembler::Success;
4031
4032 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4033 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4034 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4035 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4036 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4037 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4038
4039 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4040
4041 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4042 return MCDisassembler::Fail;
4043 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4044 return MCDisassembler::Fail;
4045 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4046 return MCDisassembler::Fail;
4047 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4048 return MCDisassembler::Fail;
4049
4050 return S;
4051 }
4052
DecodeLDRPreReg(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4053 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4054 uint64_t Address, const void *Decoder) {
4055 DecodeStatus S = MCDisassembler::Success;
4056
4057 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4058 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4059 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4060 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4061 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4062 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4063 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4064
4065 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4066 if (Rm == 0xF) S = MCDisassembler::SoftFail;
4067
4068 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4069 return MCDisassembler::Fail;
4070 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4071 return MCDisassembler::Fail;
4072 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4073 return MCDisassembler::Fail;
4074 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4075 return MCDisassembler::Fail;
4076
4077 return S;
4078 }
4079
4080
DecodeSTRPreImm(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4081 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4082 uint64_t Address, const void *Decoder) {
4083 DecodeStatus S = MCDisassembler::Success;
4084
4085 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4086 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4087 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4088 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4089 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4090 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4091
4092 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4093
4094 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4095 return MCDisassembler::Fail;
4096 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4097 return MCDisassembler::Fail;
4098 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4099 return MCDisassembler::Fail;
4100 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4101 return MCDisassembler::Fail;
4102
4103 return S;
4104 }
4105
DecodeSTRPreReg(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4106 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4107 uint64_t Address, const void *Decoder) {
4108 DecodeStatus S = MCDisassembler::Success;
4109
4110 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4111 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4112 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4113 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4114 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4115 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4116
4117 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4118
4119 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4120 return MCDisassembler::Fail;
4121 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4122 return MCDisassembler::Fail;
4123 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4124 return MCDisassembler::Fail;
4125 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4126 return MCDisassembler::Fail;
4127
4128 return S;
4129 }
4130
DecodeVLD1LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4131 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4132 uint64_t Address, const void *Decoder) {
4133 DecodeStatus S = MCDisassembler::Success;
4134
4135 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4136 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4137 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4138 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4139 unsigned size = fieldFromInstruction(Insn, 10, 2);
4140
4141 unsigned align = 0;
4142 unsigned index = 0;
4143 switch (size) {
4144 default:
4145 return MCDisassembler::Fail;
4146 case 0:
4147 if (fieldFromInstruction(Insn, 4, 1))
4148 return MCDisassembler::Fail; // UNDEFINED
4149 index = fieldFromInstruction(Insn, 5, 3);
4150 break;
4151 case 1:
4152 if (fieldFromInstruction(Insn, 5, 1))
4153 return MCDisassembler::Fail; // UNDEFINED
4154 index = fieldFromInstruction(Insn, 6, 2);
4155 if (fieldFromInstruction(Insn, 4, 1))
4156 align = 2;
4157 break;
4158 case 2:
4159 if (fieldFromInstruction(Insn, 6, 1))
4160 return MCDisassembler::Fail; // UNDEFINED
4161 index = fieldFromInstruction(Insn, 7, 1);
4162
4163 switch (fieldFromInstruction(Insn, 4, 2)) {
4164 case 0 :
4165 align = 0; break;
4166 case 3:
4167 align = 4; break;
4168 default:
4169 return MCDisassembler::Fail;
4170 }
4171 break;
4172 }
4173
4174 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4175 return MCDisassembler::Fail;
4176 if (Rm != 0xF) { // Writeback
4177 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4178 return MCDisassembler::Fail;
4179 }
4180 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4181 return MCDisassembler::Fail;
4182 Inst.addOperand(MCOperand::CreateImm(align));
4183 if (Rm != 0xF) {
4184 if (Rm != 0xD) {
4185 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4186 return MCDisassembler::Fail;
4187 } else
4188 Inst.addOperand(MCOperand::CreateReg(0));
4189 }
4190
4191 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4192 return MCDisassembler::Fail;
4193 Inst.addOperand(MCOperand::CreateImm(index));
4194
4195 return S;
4196 }
4197
DecodeVST1LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4198 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
4199 uint64_t Address, const void *Decoder) {
4200 DecodeStatus S = MCDisassembler::Success;
4201
4202 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4203 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4204 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4205 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4206 unsigned size = fieldFromInstruction(Insn, 10, 2);
4207
4208 unsigned align = 0;
4209 unsigned index = 0;
4210 switch (size) {
4211 default:
4212 return MCDisassembler::Fail;
4213 case 0:
4214 if (fieldFromInstruction(Insn, 4, 1))
4215 return MCDisassembler::Fail; // UNDEFINED
4216 index = fieldFromInstruction(Insn, 5, 3);
4217 break;
4218 case 1:
4219 if (fieldFromInstruction(Insn, 5, 1))
4220 return MCDisassembler::Fail; // UNDEFINED
4221 index = fieldFromInstruction(Insn, 6, 2);
4222 if (fieldFromInstruction(Insn, 4, 1))
4223 align = 2;
4224 break;
4225 case 2:
4226 if (fieldFromInstruction(Insn, 6, 1))
4227 return MCDisassembler::Fail; // UNDEFINED
4228 index = fieldFromInstruction(Insn, 7, 1);
4229
4230 switch (fieldFromInstruction(Insn, 4, 2)) {
4231 case 0:
4232 align = 0; break;
4233 case 3:
4234 align = 4; break;
4235 default:
4236 return MCDisassembler::Fail;
4237 }
4238 break;
4239 }
4240
4241 if (Rm != 0xF) { // Writeback
4242 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4243 return MCDisassembler::Fail;
4244 }
4245 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4246 return MCDisassembler::Fail;
4247 Inst.addOperand(MCOperand::CreateImm(align));
4248 if (Rm != 0xF) {
4249 if (Rm != 0xD) {
4250 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4251 return MCDisassembler::Fail;
4252 } else
4253 Inst.addOperand(MCOperand::CreateReg(0));
4254 }
4255
4256 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4257 return MCDisassembler::Fail;
4258 Inst.addOperand(MCOperand::CreateImm(index));
4259
4260 return S;
4261 }
4262
4263
DecodeVLD2LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4264 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
4265 uint64_t Address, const void *Decoder) {
4266 DecodeStatus S = MCDisassembler::Success;
4267
4268 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4269 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4270 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4271 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4272 unsigned size = fieldFromInstruction(Insn, 10, 2);
4273
4274 unsigned align = 0;
4275 unsigned index = 0;
4276 unsigned inc = 1;
4277 switch (size) {
4278 default:
4279 return MCDisassembler::Fail;
4280 case 0:
4281 index = fieldFromInstruction(Insn, 5, 3);
4282 if (fieldFromInstruction(Insn, 4, 1))
4283 align = 2;
4284 break;
4285 case 1:
4286 index = fieldFromInstruction(Insn, 6, 2);
4287 if (fieldFromInstruction(Insn, 4, 1))
4288 align = 4;
4289 if (fieldFromInstruction(Insn, 5, 1))
4290 inc = 2;
4291 break;
4292 case 2:
4293 if (fieldFromInstruction(Insn, 5, 1))
4294 return MCDisassembler::Fail; // UNDEFINED
4295 index = fieldFromInstruction(Insn, 7, 1);
4296 if (fieldFromInstruction(Insn, 4, 1) != 0)
4297 align = 8;
4298 if (fieldFromInstruction(Insn, 6, 1))
4299 inc = 2;
4300 break;
4301 }
4302
4303 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4304 return MCDisassembler::Fail;
4305 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4306 return MCDisassembler::Fail;
4307 if (Rm != 0xF) { // Writeback
4308 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4309 return MCDisassembler::Fail;
4310 }
4311 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4312 return MCDisassembler::Fail;
4313 Inst.addOperand(MCOperand::CreateImm(align));
4314 if (Rm != 0xF) {
4315 if (Rm != 0xD) {
4316 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4317 return MCDisassembler::Fail;
4318 } else
4319 Inst.addOperand(MCOperand::CreateReg(0));
4320 }
4321
4322 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4323 return MCDisassembler::Fail;
4324 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4325 return MCDisassembler::Fail;
4326 Inst.addOperand(MCOperand::CreateImm(index));
4327
4328 return S;
4329 }
4330
DecodeVST2LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4331 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
4332 uint64_t Address, const void *Decoder) {
4333 DecodeStatus S = MCDisassembler::Success;
4334
4335 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4336 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4337 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4338 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4339 unsigned size = fieldFromInstruction(Insn, 10, 2);
4340
4341 unsigned align = 0;
4342 unsigned index = 0;
4343 unsigned inc = 1;
4344 switch (size) {
4345 default:
4346 return MCDisassembler::Fail;
4347 case 0:
4348 index = fieldFromInstruction(Insn, 5, 3);
4349 if (fieldFromInstruction(Insn, 4, 1))
4350 align = 2;
4351 break;
4352 case 1:
4353 index = fieldFromInstruction(Insn, 6, 2);
4354 if (fieldFromInstruction(Insn, 4, 1))
4355 align = 4;
4356 if (fieldFromInstruction(Insn, 5, 1))
4357 inc = 2;
4358 break;
4359 case 2:
4360 if (fieldFromInstruction(Insn, 5, 1))
4361 return MCDisassembler::Fail; // UNDEFINED
4362 index = fieldFromInstruction(Insn, 7, 1);
4363 if (fieldFromInstruction(Insn, 4, 1) != 0)
4364 align = 8;
4365 if (fieldFromInstruction(Insn, 6, 1))
4366 inc = 2;
4367 break;
4368 }
4369
4370 if (Rm != 0xF) { // Writeback
4371 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4372 return MCDisassembler::Fail;
4373 }
4374 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4375 return MCDisassembler::Fail;
4376 Inst.addOperand(MCOperand::CreateImm(align));
4377 if (Rm != 0xF) {
4378 if (Rm != 0xD) {
4379 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4380 return MCDisassembler::Fail;
4381 } else
4382 Inst.addOperand(MCOperand::CreateReg(0));
4383 }
4384
4385 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4386 return MCDisassembler::Fail;
4387 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4388 return MCDisassembler::Fail;
4389 Inst.addOperand(MCOperand::CreateImm(index));
4390
4391 return S;
4392 }
4393
4394
DecodeVLD3LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4395 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
4396 uint64_t Address, const void *Decoder) {
4397 DecodeStatus S = MCDisassembler::Success;
4398
4399 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4400 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4401 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4402 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4403 unsigned size = fieldFromInstruction(Insn, 10, 2);
4404
4405 unsigned align = 0;
4406 unsigned index = 0;
4407 unsigned inc = 1;
4408 switch (size) {
4409 default:
4410 return MCDisassembler::Fail;
4411 case 0:
4412 if (fieldFromInstruction(Insn, 4, 1))
4413 return MCDisassembler::Fail; // UNDEFINED
4414 index = fieldFromInstruction(Insn, 5, 3);
4415 break;
4416 case 1:
4417 if (fieldFromInstruction(Insn, 4, 1))
4418 return MCDisassembler::Fail; // UNDEFINED
4419 index = fieldFromInstruction(Insn, 6, 2);
4420 if (fieldFromInstruction(Insn, 5, 1))
4421 inc = 2;
4422 break;
4423 case 2:
4424 if (fieldFromInstruction(Insn, 4, 2))
4425 return MCDisassembler::Fail; // UNDEFINED
4426 index = fieldFromInstruction(Insn, 7, 1);
4427 if (fieldFromInstruction(Insn, 6, 1))
4428 inc = 2;
4429 break;
4430 }
4431
4432 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4433 return MCDisassembler::Fail;
4434 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4435 return MCDisassembler::Fail;
4436 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4437 return MCDisassembler::Fail;
4438
4439 if (Rm != 0xF) { // Writeback
4440 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4441 return MCDisassembler::Fail;
4442 }
4443 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4444 return MCDisassembler::Fail;
4445 Inst.addOperand(MCOperand::CreateImm(align));
4446 if (Rm != 0xF) {
4447 if (Rm != 0xD) {
4448 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4449 return MCDisassembler::Fail;
4450 } else
4451 Inst.addOperand(MCOperand::CreateReg(0));
4452 }
4453
4454 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4455 return MCDisassembler::Fail;
4456 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4457 return MCDisassembler::Fail;
4458 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4459 return MCDisassembler::Fail;
4460 Inst.addOperand(MCOperand::CreateImm(index));
4461
4462 return S;
4463 }
4464
DecodeVST3LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4465 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
4466 uint64_t Address, const void *Decoder) {
4467 DecodeStatus S = MCDisassembler::Success;
4468
4469 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4470 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4471 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4472 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4473 unsigned size = fieldFromInstruction(Insn, 10, 2);
4474
4475 unsigned align = 0;
4476 unsigned index = 0;
4477 unsigned inc = 1;
4478 switch (size) {
4479 default:
4480 return MCDisassembler::Fail;
4481 case 0:
4482 if (fieldFromInstruction(Insn, 4, 1))
4483 return MCDisassembler::Fail; // UNDEFINED
4484 index = fieldFromInstruction(Insn, 5, 3);
4485 break;
4486 case 1:
4487 if (fieldFromInstruction(Insn, 4, 1))
4488 return MCDisassembler::Fail; // UNDEFINED
4489 index = fieldFromInstruction(Insn, 6, 2);
4490 if (fieldFromInstruction(Insn, 5, 1))
4491 inc = 2;
4492 break;
4493 case 2:
4494 if (fieldFromInstruction(Insn, 4, 2))
4495 return MCDisassembler::Fail; // UNDEFINED
4496 index = fieldFromInstruction(Insn, 7, 1);
4497 if (fieldFromInstruction(Insn, 6, 1))
4498 inc = 2;
4499 break;
4500 }
4501
4502 if (Rm != 0xF) { // Writeback
4503 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4504 return MCDisassembler::Fail;
4505 }
4506 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4507 return MCDisassembler::Fail;
4508 Inst.addOperand(MCOperand::CreateImm(align));
4509 if (Rm != 0xF) {
4510 if (Rm != 0xD) {
4511 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4512 return MCDisassembler::Fail;
4513 } else
4514 Inst.addOperand(MCOperand::CreateReg(0));
4515 }
4516
4517 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4518 return MCDisassembler::Fail;
4519 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4520 return MCDisassembler::Fail;
4521 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4522 return MCDisassembler::Fail;
4523 Inst.addOperand(MCOperand::CreateImm(index));
4524
4525 return S;
4526 }
4527
4528
DecodeVLD4LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4529 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4530 uint64_t Address, const void *Decoder) {
4531 DecodeStatus S = MCDisassembler::Success;
4532
4533 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4534 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4535 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4536 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4537 unsigned size = fieldFromInstruction(Insn, 10, 2);
4538
4539 unsigned align = 0;
4540 unsigned index = 0;
4541 unsigned inc = 1;
4542 switch (size) {
4543 default:
4544 return MCDisassembler::Fail;
4545 case 0:
4546 if (fieldFromInstruction(Insn, 4, 1))
4547 align = 4;
4548 index = fieldFromInstruction(Insn, 5, 3);
4549 break;
4550 case 1:
4551 if (fieldFromInstruction(Insn, 4, 1))
4552 align = 8;
4553 index = fieldFromInstruction(Insn, 6, 2);
4554 if (fieldFromInstruction(Insn, 5, 1))
4555 inc = 2;
4556 break;
4557 case 2:
4558 switch (fieldFromInstruction(Insn, 4, 2)) {
4559 case 0:
4560 align = 0; break;
4561 case 3:
4562 return MCDisassembler::Fail;
4563 default:
4564 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4565 }
4566
4567 index = fieldFromInstruction(Insn, 7, 1);
4568 if (fieldFromInstruction(Insn, 6, 1))
4569 inc = 2;
4570 break;
4571 }
4572
4573 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4574 return MCDisassembler::Fail;
4575 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4576 return MCDisassembler::Fail;
4577 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4578 return MCDisassembler::Fail;
4579 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4580 return MCDisassembler::Fail;
4581
4582 if (Rm != 0xF) { // Writeback
4583 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4584 return MCDisassembler::Fail;
4585 }
4586 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4587 return MCDisassembler::Fail;
4588 Inst.addOperand(MCOperand::CreateImm(align));
4589 if (Rm != 0xF) {
4590 if (Rm != 0xD) {
4591 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4592 return MCDisassembler::Fail;
4593 } else
4594 Inst.addOperand(MCOperand::CreateReg(0));
4595 }
4596
4597 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4598 return MCDisassembler::Fail;
4599 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4600 return MCDisassembler::Fail;
4601 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4602 return MCDisassembler::Fail;
4603 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4604 return MCDisassembler::Fail;
4605 Inst.addOperand(MCOperand::CreateImm(index));
4606
4607 return S;
4608 }
4609
DecodeVST4LN(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4610 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4611 uint64_t Address, const void *Decoder) {
4612 DecodeStatus S = MCDisassembler::Success;
4613
4614 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4615 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4616 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4617 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4618 unsigned size = fieldFromInstruction(Insn, 10, 2);
4619
4620 unsigned align = 0;
4621 unsigned index = 0;
4622 unsigned inc = 1;
4623 switch (size) {
4624 default:
4625 return MCDisassembler::Fail;
4626 case 0:
4627 if (fieldFromInstruction(Insn, 4, 1))
4628 align = 4;
4629 index = fieldFromInstruction(Insn, 5, 3);
4630 break;
4631 case 1:
4632 if (fieldFromInstruction(Insn, 4, 1))
4633 align = 8;
4634 index = fieldFromInstruction(Insn, 6, 2);
4635 if (fieldFromInstruction(Insn, 5, 1))
4636 inc = 2;
4637 break;
4638 case 2:
4639 switch (fieldFromInstruction(Insn, 4, 2)) {
4640 case 0:
4641 align = 0; break;
4642 case 3:
4643 return MCDisassembler::Fail;
4644 default:
4645 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4646 }
4647
4648 index = fieldFromInstruction(Insn, 7, 1);
4649 if (fieldFromInstruction(Insn, 6, 1))
4650 inc = 2;
4651 break;
4652 }
4653
4654 if (Rm != 0xF) { // Writeback
4655 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4656 return MCDisassembler::Fail;
4657 }
4658 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4659 return MCDisassembler::Fail;
4660 Inst.addOperand(MCOperand::CreateImm(align));
4661 if (Rm != 0xF) {
4662 if (Rm != 0xD) {
4663 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4664 return MCDisassembler::Fail;
4665 } else
4666 Inst.addOperand(MCOperand::CreateReg(0));
4667 }
4668
4669 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4670 return MCDisassembler::Fail;
4671 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4672 return MCDisassembler::Fail;
4673 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4674 return MCDisassembler::Fail;
4675 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4676 return MCDisassembler::Fail;
4677 Inst.addOperand(MCOperand::CreateImm(index));
4678
4679 return S;
4680 }
4681
DecodeVMOVSRR(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4682 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4683 uint64_t Address, const void *Decoder) {
4684 DecodeStatus S = MCDisassembler::Success;
4685 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4686 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4687 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4688 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4689 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4690
4691 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4692 S = MCDisassembler::SoftFail;
4693
4694 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4695 return MCDisassembler::Fail;
4696 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4697 return MCDisassembler::Fail;
4698 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4699 return MCDisassembler::Fail;
4700 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4701 return MCDisassembler::Fail;
4702 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4703 return MCDisassembler::Fail;
4704
4705 return S;
4706 }
4707
DecodeVMOVRRS(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4708 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4709 uint64_t Address, const void *Decoder) {
4710 DecodeStatus S = MCDisassembler::Success;
4711 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4712 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4713 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4714 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4715 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4716
4717 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4718 S = MCDisassembler::SoftFail;
4719
4720 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4721 return MCDisassembler::Fail;
4722 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4723 return MCDisassembler::Fail;
4724 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4725 return MCDisassembler::Fail;
4726 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4727 return MCDisassembler::Fail;
4728 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4729 return MCDisassembler::Fail;
4730
4731 return S;
4732 }
4733
DecodeIT(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4734 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4735 uint64_t Address, const void *Decoder) {
4736 DecodeStatus S = MCDisassembler::Success;
4737 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4738 unsigned mask = fieldFromInstruction(Insn, 0, 4);
4739
4740 if (pred == 0xF) {
4741 pred = 0xE;
4742 S = MCDisassembler::SoftFail;
4743 }
4744
4745 if (mask == 0x0)
4746 return MCDisassembler::Fail;
4747
4748 Inst.addOperand(MCOperand::CreateImm(pred));
4749 Inst.addOperand(MCOperand::CreateImm(mask));
4750 return S;
4751 }
4752
4753 static DecodeStatus
DecodeT2LDRDPreInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4754 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4755 uint64_t Address, const void *Decoder) {
4756 DecodeStatus S = MCDisassembler::Success;
4757
4758 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4759 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4760 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4761 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4762 unsigned W = fieldFromInstruction(Insn, 21, 1);
4763 unsigned U = fieldFromInstruction(Insn, 23, 1);
4764 unsigned P = fieldFromInstruction(Insn, 24, 1);
4765 bool writeback = (W == 1) | (P == 0);
4766
4767 addr |= (U << 8) | (Rn << 9);
4768
4769 if (writeback && (Rn == Rt || Rn == Rt2))
4770 Check(S, MCDisassembler::SoftFail);
4771 if (Rt == Rt2)
4772 Check(S, MCDisassembler::SoftFail);
4773
4774 // Rt
4775 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4776 return MCDisassembler::Fail;
4777 // Rt2
4778 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4779 return MCDisassembler::Fail;
4780 // Writeback operand
4781 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4782 return MCDisassembler::Fail;
4783 // addr
4784 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4785 return MCDisassembler::Fail;
4786
4787 return S;
4788 }
4789
4790 static DecodeStatus
DecodeT2STRDPreInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4791 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
4792 uint64_t Address, const void *Decoder) {
4793 DecodeStatus S = MCDisassembler::Success;
4794
4795 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4796 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4797 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4798 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4799 unsigned W = fieldFromInstruction(Insn, 21, 1);
4800 unsigned U = fieldFromInstruction(Insn, 23, 1);
4801 unsigned P = fieldFromInstruction(Insn, 24, 1);
4802 bool writeback = (W == 1) | (P == 0);
4803
4804 addr |= (U << 8) | (Rn << 9);
4805
4806 if (writeback && (Rn == Rt || Rn == Rt2))
4807 Check(S, MCDisassembler::SoftFail);
4808
4809 // Writeback operand
4810 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4811 return MCDisassembler::Fail;
4812 // Rt
4813 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4814 return MCDisassembler::Fail;
4815 // Rt2
4816 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4817 return MCDisassembler::Fail;
4818 // addr
4819 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4820 return MCDisassembler::Fail;
4821
4822 return S;
4823 }
4824
DecodeT2Adr(MCInst & Inst,uint32_t Insn,uint64_t Address,const void * Decoder)4825 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
4826 uint64_t Address, const void *Decoder) {
4827 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
4828 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
4829 if (sign1 != sign2) return MCDisassembler::Fail;
4830
4831 unsigned Val = fieldFromInstruction(Insn, 0, 8);
4832 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
4833 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
4834 Val |= sign1 << 12;
4835 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4836
4837 return MCDisassembler::Success;
4838 }
4839
DecodeT2ShifterImmOperand(MCInst & Inst,uint32_t Val,uint64_t Address,const void * Decoder)4840 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
4841 uint64_t Address,
4842 const void *Decoder) {
4843 DecodeStatus S = MCDisassembler::Success;
4844
4845 // Shift of "asr #32" is not allowed in Thumb2 mode.
4846 if (Val == 0x20) S = MCDisassembler::SoftFail;
4847 Inst.addOperand(MCOperand::CreateImm(Val));
4848 return S;
4849 }
4850
DecodeSwap(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4851 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
4852 uint64_t Address, const void *Decoder) {
4853 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4854 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
4855 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4856 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4857
4858 if (pred == 0xF)
4859 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4860
4861 DecodeStatus S = MCDisassembler::Success;
4862
4863 if (Rt == Rn || Rn == Rt2)
4864 S = MCDisassembler::SoftFail;
4865
4866 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4867 return MCDisassembler::Fail;
4868 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4869 return MCDisassembler::Fail;
4870 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4871 return MCDisassembler::Fail;
4872 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4873 return MCDisassembler::Fail;
4874
4875 return S;
4876 }
4877
DecodeVCVTD(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4878 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
4879 uint64_t Address, const void *Decoder) {
4880 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4881 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4882 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4883 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4884 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4885 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
4886 unsigned op = fieldFromInstruction(Insn, 5, 1);
4887
4888 DecodeStatus S = MCDisassembler::Success;
4889
4890 // VMOVv2f32 is ambiguous with these decodings.
4891 if (!(imm & 0x38) && cmode == 0xF) {
4892 if (op == 1) return MCDisassembler::Fail;
4893 Inst.setOpcode(ARM::VMOVv2f32);
4894 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4895 }
4896
4897 if (!(imm & 0x20)) return MCDisassembler::Fail;
4898
4899 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4900 return MCDisassembler::Fail;
4901 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
4902 return MCDisassembler::Fail;
4903 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4904
4905 return S;
4906 }
4907
DecodeVCVTQ(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)4908 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
4909 uint64_t Address, const void *Decoder) {
4910 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4911 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4912 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4913 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4914 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4915 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
4916 unsigned op = fieldFromInstruction(Insn, 5, 1);
4917
4918 DecodeStatus S = MCDisassembler::Success;
4919
4920 // VMOVv4f32 is ambiguous with these decodings.
4921 if (!(imm & 0x38) && cmode == 0xF) {
4922 if (op == 1) return MCDisassembler::Fail;
4923 Inst.setOpcode(ARM::VMOVv4f32);
4924 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4925 }
4926
4927 if (!(imm & 0x20)) return MCDisassembler::Fail;
4928
4929 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
4930 return MCDisassembler::Fail;
4931 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
4932 return MCDisassembler::Fail;
4933 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4934
4935 return S;
4936 }
4937
DecodeLDR(MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4938 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
4939 uint64_t Address, const void *Decoder) {
4940 DecodeStatus S = MCDisassembler::Success;
4941
4942 unsigned Rn = fieldFromInstruction(Val, 16, 4);
4943 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4944 unsigned Rm = fieldFromInstruction(Val, 0, 4);
4945 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
4946 unsigned Cond = fieldFromInstruction(Val, 28, 4);
4947
4948 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
4949 S = MCDisassembler::SoftFail;
4950
4951 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4952 return MCDisassembler::Fail;
4953 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4954 return MCDisassembler::Fail;
4955 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
4956 return MCDisassembler::Fail;
4957 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
4958 return MCDisassembler::Fail;
4959 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
4960 return MCDisassembler::Fail;
4961
4962 return S;
4963 }
4964
DecodeMRRC2(llvm::MCInst & Inst,unsigned Val,uint64_t Address,const void * Decoder)4965 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
4966 uint64_t Address, const void *Decoder) {
4967
4968 DecodeStatus S = MCDisassembler::Success;
4969
4970 unsigned CRm = fieldFromInstruction(Val, 0, 4);
4971 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
4972 unsigned cop = fieldFromInstruction(Val, 8, 4);
4973 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4974 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
4975
4976 if ((cop & ~0x1) == 0xa)
4977 return MCDisassembler::Fail;
4978
4979 if (Rt == Rt2)
4980 S = MCDisassembler::SoftFail;
4981
4982 Inst.addOperand(MCOperand::CreateImm(cop));
4983 Inst.addOperand(MCOperand::CreateImm(opc1));
4984 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4985 return MCDisassembler::Fail;
4986 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4987 return MCDisassembler::Fail;
4988 Inst.addOperand(MCOperand::CreateImm(CRm));
4989
4990 return S;
4991 }
4992
4993