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Searched refs:INVALID_SREG (Results 1 – 14 of 14) sorted by relevance

/art/compiler/dex/quick/arm64/
Darm64_lir.h189 {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, rs_w0, INVALID_SREG, INVALID_SREG};
191 {kLocPhysReg, 0, 0, 0, 0, 0, 1, 0, 1, rs_x0, INVALID_SREG, INVALID_SREG};
193 {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, rs_x0, INVALID_SREG, INVALID_SREG};
195 {kLocPhysReg, 0, 0, 0, 1, 0, 0, 0, 1, rs_f0, INVALID_SREG, INVALID_SREG};
197 {kLocPhysReg, 1, 0, 0, 1, 0, 0, 0, 1, rs_d0, INVALID_SREG, INVALID_SREG};
/art/compiler/dex/quick/x86/
Dx86_lir.h354 RegStorage(RegStorage::k32BitSolo, rAX), INVALID_SREG, INVALID_SREG};
357 RegStorage(RegStorage::k64BitPair, rAX, rDX), INVALID_SREG, INVALID_SREG};
360 RegStorage(RegStorage::k32BitSolo, rAX), INVALID_SREG, INVALID_SREG};
363 RegStorage(RegStorage::k64BitSolo, rAX), INVALID_SREG, INVALID_SREG};
366 RegStorage(RegStorage::k64BitSolo, rAX), INVALID_SREG, INVALID_SREG};
369 RegStorage(RegStorage::k32BitSolo, fr0), INVALID_SREG, INVALID_SREG};
372 RegStorage(RegStorage::k64BitSolo, dr0), INVALID_SREG, INVALID_SREG};
Dfp_x86.cc604 DCHECK_NE(rl_src.s_reg_low, INVALID_SREG); in GenInlinedAbsFloat()
605 if (rl_dest.s_reg_low == INVALID_SREG) { in GenInlinedAbsFloat()
646 DCHECK_NE(rl_src.s_reg_low, INVALID_SREG); in GenInlinedAbsDouble()
647 if (rl_dest.s_reg_low == INVALID_SREG) { in GenInlinedAbsDouble()
Dint_x86.cc680 rl_result = {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, rs_r2, INVALID_SREG, INVALID_SREG}; in GenDivRemLit()
795 RegLocation rl_result = {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, rs_r0, INVALID_SREG, INVALID_SREG}; in GenDivRem()
1440 RegStorage::MakeRegPair(rs_r0, rs_r2), INVALID_SREG, INVALID_SREG}; in GenMulLongConst()
1578 RegStorage::MakeRegPair(rs_r0, rs_r2), INVALID_SREG, INVALID_SREG}; in GenMulLong()
1833 … RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, rs_r2q, INVALID_SREG, INVALID_SREG}; in GenDivRemLongLit()
1990 RegLocation rl_result = {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, rs_r0q, INVALID_SREG, INVALID_SREG}; in GenDivRemLong()
/art/compiler/dex/quick/
Dgen_loadstore.cc161 DCHECK_NE(rl_src.s_reg_low, INVALID_SREG); in LoadValue()
180 DCHECK((live_sreg_ == INVALID_SREG) || in StoreValue()
248 DCHECK_NE(rl_src.s_reg_low, INVALID_SREG); in LoadValueWide()
249 DCHECK_NE(GetSRegHi(rl_src.s_reg_low), INVALID_SREG); in LoadValueWide()
264 DCHECK((live_sreg_ == INVALID_SREG) || in StoreValueWide()
401 loc.s_reg_low = INVALID_SREG; in ForceTemp()
436 loc.s_reg_low = INVALID_SREG; in ForceTempWide()
Dralloc_util.cc37 live_sreg_ = INVALID_SREG; in ResetRegPool()
43 s_reg_(INVALID_SREG), def_use_mask_(mask), master_(this), def_start_(nullptr), in RegisterInfo()
221 if (s_reg != INVALID_SREG) { in ClobberSReg()
223 live_sreg_ = INVALID_SREG; in ClobberSReg()
365 if (info->SReg() != INVALID_SREG) { in AllocTempBody()
827 if (s_reg == INVALID_SREG) { in MarkLive()
951 if (info->IsTemp() && info->IsLive() && info->IsWide() && my_sreg != INVALID_SREG) { in CheckCorePoolSanity()
965 if (info->IsLive() && (info->SReg() != INVALID_SREG)) { in CheckCorePoolSanity()
967 DCHECK_EQ(info->Master()->SReg(), INVALID_SREG); in CheckCorePoolSanity()
975 if (info->IsLive() && (info->SReg() != INVALID_SREG)) { in CheckCorePoolSanity()
[all …]
Dmir_to_lir.h137 #ifndef INVALID_SREG
138 #define INVALID_SREG (-1) macro
369 if (SReg() != INVALID_SREG) { in MarkDead()
370 s_reg_ = INVALID_SREG; in MarkDead()
391 int SReg() { return (!IsTemp() || IsLive()) ? s_reg_ : INVALID_SREG; } in SReg()
Dmir_to_lir-inl.h29 if (p->SReg() != INVALID_SREG) { in ClobberBody()
Dmir_to_lir.cc1152 live_sreg_ = INVALID_SREG; in MethodBlockCodeGen()
/art/compiler/dex/quick/mips/
Dmips_lir.h355 RegStorage(RegStorage::k32BitSolo, rV0), INVALID_SREG, INVALID_SREG};
358 RegStorage(RegStorage::k64BitPair, rV0, rV1), INVALID_SREG, INVALID_SREG};
361 RegStorage(RegStorage::k32BitSolo, rF0), INVALID_SREG, INVALID_SREG};
365 RegStorage(RegStorage::k64BitPair, rF0, rF1), INVALID_SREG, INVALID_SREG};
/art/compiler/dex/quick/arm/
Darm_lir.h303 RegStorage(RegStorage::k32BitSolo, r0), INVALID_SREG, INVALID_SREG};
306 RegStorage(RegStorage::k64BitPair, r0, r1), INVALID_SREG, INVALID_SREG};
309 RegStorage(RegStorage::k32BitSolo, r0), INVALID_SREG, INVALID_SREG};
312 RegStorage(RegStorage::k64BitPair, r0, r1), INVALID_SREG, INVALID_SREG};
/art/compiler/dex/
Dvreg_analysis.cc436 RegStorage(), INVALID_SREG, INVALID_SREG};
Dmir_graph.h183 #define INVALID_SREG (-1) macro
536 const RegLocation bad_loc = {kLocDalvikFrame, 0, 0, 0, 0, 0, 0, 0, 0, RegStorage(), INVALID_SREG,
537 INVALID_SREG};
Dmir_optimization.cc246 RegStorage(), INVALID_SREG, INVALID_SREG};