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/art/runtime/arch/arm64/
Dmemcmp16_arm64.S28 #define src1 x0 macro
53 eor tmp1, src1, src2
56 ands tmp1, src1, #7
62 ldr data1, [src1], #8
109 bic src1, src1, #7
113 ldr data1, [src1], #8
134 ldrh data1w, [src1], #2
/art/compiler/dex/quick/
Dmir_to_lir-inl.h89 inline LIR* Mir2Lir::NewLIR2(int opcode, int dest, int src1) { in NewLIR2() argument
94 LIR* insn = RawLIR(current_dalvik_offset_, opcode, dest, src1); in NewLIR2()
109 inline LIR* Mir2Lir::NewLIR3(int opcode, int dest, int src1, int src2) { in NewLIR3() argument
114 LIR* insn = RawLIR(current_dalvik_offset_, opcode, dest, src1, src2); in NewLIR3()
119 inline LIR* Mir2Lir::NewLIR4(int opcode, int dest, int src1, int src2, int info) { in NewLIR4() argument
124 LIR* insn = RawLIR(current_dalvik_offset_, opcode, dest, src1, src2, info); in NewLIR4()
129 inline LIR* Mir2Lir::NewLIR5(int opcode, int dest, int src1, int src2, int info1, in NewLIR5() argument
135 LIR* insn = RawLIR(current_dalvik_offset_, opcode, dest, src1, src2, info1, info2); in NewLIR5()
Dcodegen_util.cc915 bool Mir2Lir::EvaluateBranch(Instruction::Code opcode, int32_t src1, int32_t src2) { in EvaluateBranch() argument
918 case Instruction::IF_EQ: is_taken = (src1 == src2); break; in EvaluateBranch()
919 case Instruction::IF_NE: is_taken = (src1 != src2); break; in EvaluateBranch()
920 case Instruction::IF_LT: is_taken = (src1 < src2); break; in EvaluateBranch()
921 case Instruction::IF_GE: is_taken = (src1 >= src2); break; in EvaluateBranch()
922 case Instruction::IF_GT: is_taken = (src1 > src2); break; in EvaluateBranch()
923 case Instruction::IF_LE: is_taken = (src1 <= src2); break; in EvaluateBranch()
924 case Instruction::IF_EQZ: is_taken = (src1 == 0); break; in EvaluateBranch()
925 case Instruction::IF_NEZ: is_taken = (src1 != 0); break; in EvaluateBranch()
926 case Instruction::IF_LTZ: is_taken = (src1 < 0); break; in EvaluateBranch()
[all …]
Dmir_to_lir.h680 LIR* NewLIR2(int opcode, int dest, int src1);
682 LIR* NewLIR3(int opcode, int dest, int src1, int src2);
683 LIR* NewLIR4(int opcode, int dest, int src1, int src2, int info);
684 LIR* NewLIR5(int opcode, int dest, int src1, int src2, int info1, int info2);
696 bool EvaluateBranch(Instruction::Code opcode, int src1, int src2);
1384 virtual LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) = 0;
/art/compiler/dex/portable/
Dmir_to_gbc.cc314 ::llvm::Value* src1, ::llvm::Value* src2) { in ConvertCompare() argument
316 DCHECK_EQ(src1->getType(), src2->getType()); in ConvertCompare()
318 case kCondEq: res = irb_->CreateICmpEQ(src1, src2); break; in ConvertCompare()
319 case kCondNe: res = irb_->CreateICmpNE(src1, src2); break; in ConvertCompare()
320 case kCondLt: res = irb_->CreateICmpSLT(src1, src2); break; in ConvertCompare()
321 case kCondGe: res = irb_->CreateICmpSGE(src1, src2); break; in ConvertCompare()
322 case kCondGt: res = irb_->CreateICmpSGT(src1, src2); break; in ConvertCompare()
323 case kCondLe: res = irb_->CreateICmpSLE(src1, src2); break; in ConvertCompare()
334 ::llvm::Value* src1 = GetLLVMValue(rl_src1.orig_sreg); in ConvertCompareAndBranch()
336 ::llvm::Value* cond_value = ConvertCompare(cc, src1, src2); in ConvertCompareAndBranch()
[all …]
Dmir_to_gbc.h116 ::llvm::Value* src1, ::llvm::Value* src2);
121 ::llvm::Value* GenDivModOp(bool is_div, bool is_long, ::llvm::Value* src1,
123 ::llvm::Value* GenArithOp(OpKind op, bool is_long, ::llvm::Value* src1,
/art/compiler/dex/
Dssa_transformation.cc438 void MIRGraph::ComputeSuccLineIn(ArenaBitVector* dest, const ArenaBitVector* src1, in ComputeSuccLineIn() argument
440 if (dest->GetStorageSize() != src1->GetStorageSize() || in ComputeSuccLineIn()
442 dest->IsExpandable() != src1->IsExpandable() || in ComputeSuccLineIn()
449 dest->GetRawStorage()[idx] |= src1->GetRawStorageWord(idx) & ~(src2->GetRawStorageWord(idx)); in ComputeSuccLineIn()
Dmir_graph.h1082 void ComputeSuccLineIn(ArenaBitVector* dest, const ArenaBitVector* src1,
Dglobal_value_numbering_test.cc128 #define DEF_PHI2(bb, reg, src1, src2) \ argument
129 { bb, static_cast<Instruction::Code>(kMirOpPhi), 0, 0u, 2u, { src1, src2 }, 1, { reg } }
/art/compiler/dex/quick/mips/
Dint_mips.cc65 LIR* MipsMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch() argument
116 branch = NewLIR2(br_op, src1.GetReg(), src2.GetReg()); in OpCmpBranch()
120 NewLIR3(slt_op, t_reg.GetReg(), src2.GetReg(), src1.GetReg()); in OpCmpBranch()
122 NewLIR3(slt_op, t_reg.GetReg(), src1.GetReg(), src2.GetReg()); in OpCmpBranch()
Dcodegen_mips.h137 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
/art/compiler/dex/quick/arm/
Dcodegen_arm.h139 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
Dint_arm.cc28 LIR* ArmMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch() argument
29 OpRegReg(kOpCmp, src1, src2); in OpCmpBranch()
/art/compiler/dex/quick/arm64/
Dcodegen_arm64.h205 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) OVERRIDE;
Dint_arm64.cc29 LIR* Arm64Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch() argument
30 OpRegReg(kOpCmp, src1, src2); in OpCmpBranch()
/art/compiler/dex/quick/x86/
Dcodegen_x86.h264 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) OVERRIDE;
Dint_x86.cc96 LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch() argument
97 NewLIR2(src1.Is64Bit() ? kX86Cmp64RR : kX86Cmp32RR, src1.GetReg(), src2.GetReg()); in OpCmpBranch()