| /external/linux-tools-perf/perf-3.12.0/arch/metag/lib/ |
| D | memcpy.S | 33 ANDS D1Ar5, D1Ar1, #7 ! test destination alignment
54 ANDS D0Ar4, D0Ar4, #7 ! test source alignment
75 ANDS D1Ar3, D1Ar3, #0x1f
176 ANDS D1Ar3, D1Ar3, #7
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| D | memset.S | 13 ANDS D0Ar4,D1Ar1,#7 ! Extract bottom LSBs of dst
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| /external/vixl/src/a64/ |
| D | constants-a64.h | 396 ANDS = 0x60000000, enumerator
397 BICS = ANDS | NOT
411 ANDS_w_imm = LogicalImmediateFixed | ANDS,
412 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits
438 ANDS_w = LogicalShiftedFixed | ANDS,
439 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits,
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| D | instructions-a64.h | 265 if (Mask(LogicalImmediateMask & LogicalOpMask) == ANDS) { in RdMode()
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| D | macro-assembler-a64.cc | 61 LogicalMacro(rd, rn, operand, ANDS); in Ands()
150 case ANDS: // Fall through. in LogicalMacro()
168 case ANDS: // Fall through. in LogicalMacro()
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| D | assembler-a64.cc | 648 Logical(rd, rn, operand, ANDS); in ands()
1687 Instr dest_reg = (op == ANDS) ? Rd(rd) : RdSP(rd); in LogicalImmediate()
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| D | simulator-a64.cc | 691 case ANDS: update_flags = true; // Fall through. in LogicalHelper()
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-ands-bad-peephole.ll | 2 ; Check that ANDS (tst) is not merged with ADD when the immediate
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| /external/chromium_org/v8/src/arm64/ |
| D | constants-arm64.h | 504 ANDS = 0x60000000, enumerator
505 BICS = ANDS | NOT
519 ANDS_w_imm = LogicalImmediateFixed | ANDS,
520 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits
546 ANDS_w = LogicalShiftedFixed | ANDS,
547 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits,
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| D | instructions-arm64.h | 238 if (Mask(LogicalImmediateMask & LogicalOpMask) == ANDS) { in RdMode()
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| D | macro-assembler-arm64-inl.h | 59 LogicalMacro(rd, rn, operand, ANDS); in Ands()
66 LogicalMacro(AppropriateZeroRegFor(rn), rn, operand, ANDS); in Tst()
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| D | assembler-arm64.cc | 960 Logical(rd, rn, operand, ANDS); in ands()
2053 Instr dest_reg = (op == ANDS) ? Rd(rd) : RdSP(rd); in LogicalImmediate()
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| D | macro-assembler-arm64.cc | 88 case ANDS: // Fall through. in LogicalMacro()
106 case ANDS: // Fall through. in LogicalMacro()
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| D | simulator-arm64.cc | 1373 case ANDS: update_flags = true; // Fall through. in LogicalHelper()
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| /external/llvm/test/MC/ARM/ |
| D | thumb2-narrow-dp.ll | 15 ANDS r0, r2, r1 // Must be wide - 3 distinct registers
16 ANDS r2, r2, r1 // Should choose narrow
17 ANDS r2, r1, r2 // Should choose narrow - commutative
18 ANDS.W r0, r0, r1 // Explicitly wide
19 ANDS.W r3, r1, r3
21 ANDS r7, r7, r1 // Should use narrow
22 ANDS r7, r1, r7 // Commutative
23 ANDS r8, r1, r8 // high registers so must use wide encoding
24 ANDS r8, r8, r1
25 ANDS r0, r8, r0
[all …]
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| /external/llvm/test/CodeGen/ARM/ |
| D | arm-and-tst-peephole.ll | 81 ; generates a predicated ANDS instruction. Check that the predicate is printed
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 58 ANDS, enumerator
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| D | AArch64InstrInfo.td | 142 def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,
674 defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">;
689 defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
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| D | AArch64ISelLowering.cpp | 664 case AArch64ISD::ANDS: return "AArch64ISD::ANDS"; in getTargetNodeName()
1007 Opcode = AArch64ISD::ANDS; in emitComparison()
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| /external/srec/config/en.us/dictionary/ |
| D | c0.6 | 3710 ANDS AE1 N D Z
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